MT91L62

更新时间： 2024-01-24 15:32:44

品牌	Logo	应用领域
加拿大卓联 - ZARLINK		解码器编解码器
页数	文件大小	规格书
19页	405K
描述
3 Volt Single Rail Codec

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技术参数
数据手册

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MT91L62 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	DIP, DIP20,.3	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.36
Is Samacsys：	N	压伸定律：	A/MU-LAW
滤波器：	YES	最大增益公差：	1.6 dB
JESD-30 代码：	R-PDIP-T20	JESD-609代码：	e0
长度：	25.195 mm	线性编码：	NOT AVAILABLE
功能数量：	1	端子数量：	20
工作模式：	SYNCHRONOUS/ASYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP	封装等效代码：	DIP20,.3
封装形状：	RECTANGULAR	封装形式：	IN-LINE
峰值回流温度（摄氏度）：	225	电源：	3 V
认证状态：	Not Qualified	座面最大高度：	5.33 mm
子类别：	Codecs	最大压摆率：	0.01 mA
标称供电电压：	3 V	表面贴装：	NO
技术：	CMOS	电信集成电路类型：	PROGRAMMABLE CODEC
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	30
宽度：	7.62 mm	Base Number Matches：	1

MT91L62 数据手册

MT91L62

Data Sheet

Analog Interfaces

Standard interfaces are provided by the MT91L62. These are:

•

The analog inputs (transmitter), pins AIN+/AIN-. The maximum peak to peak input is 2.123 Vpp µ−law

across AIN+/AIN- and 2.2 Vpp A-law across these pins.

The analog outputs (receiver), pins AOUT+/AOUT-.This internally compensated fully differential output

driver is capable of driving a load of 20 k ohms.

PCM Serial Interface

A serial link is required to transport data between the MT91L62 and an external digital transmission device. The

MT91L62 utilizes the strobed data interface found on many standard Codec devices. This interface is commonly

referred to as Simple Serial Interface (SSI).

The bit clock rate is selected by setting the CSL2-0 control pins as shown in Figure 2.

Quiet Code

The PCM serial port can be made to send quiet code to the decoder and receive filter path by setting the RxMute

pin high. Likewise, the PCM serial port will send quiet code in the transmit path when the TxMute pin is high. When

either of these pins are low their respective paths function normally. The -Zero entry of Table 1 is used for the quiet

code definition.

ExternalClock

Bit Rate (kHz)

CLOCKin

(kHz)

CSL₂

CSL₁

CSL₀

128

256

4096

512

1536

2048

4096

1536

2048

4096

Table 2 - Bit Clock Rate Selection

SSI Mode

The SSI BUS consists of input and output serial data streams named Din and Dout respectively, a Clock input

signal (CLOCKin), and a framing strobe input (STB). A 4.096 MHz master clock is also required for SSI operation if

the bit clock is less than 512 kHz. The timing requirements for SSI are shown in Figures 5 & 6.

In SSI mode the MT91L62 supports only B-Channel operation. Hence, in SSI mode transmit and receive B-Channel

data are always in the channel defined by the STB input.

The data strobe input STB determines the 8-bit timeslot used by the device for both transmit and receive data. This

is an active high signal with an 8 kHz repetition rate.

SSI operation is separated into two categories based upon the data rate of the available bit clock. If the bit clock is

512 kHz or greater then it is used directly by the internal MT91L62 functions allowing synchronous operation. If the

available bit clock is 128 kHz or 256 kHz, then a 4096 kHz master clock is required to derive clocks for the internal

MT91L62 functions.

Zarlink Semiconductor Inc.

1 2 345 6 7...19

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与MT91L62相关器件

型号	品牌	描述	获取价格	数据表
MT91L62AE	MITEL	ISO2-CMOS 3 Volt Single Rail Codec	获取价格
MT91L62AE	ZARLINK	3 Volt Single Rail Codec	获取价格
MT91L62AN	ZARLINK	3 Volt Single Rail Codec	获取价格
MT91L62AN	MITEL	ISO2-CMOS 3 Volt Single Rail Codec	获取价格
MT91L62AS	MITEL	ISO2-CMOS 3 Volt Single Rail Codec	获取价格
MT91L62AS	ZARLINK	3 Volt Single Rail Codec	获取价格

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