MT91L60/61
Data Sheet
Functional Description
Filter/Codec
The Filter/Codec block implements conversion of the analog 0-3.3 kHz speech signals to/from the digital domain
compatible with 64 kb/s PCM B-Channels. Selection of companding curves and digital code assignment are
programmable. These are ITU-T G.711 A-law or µ-Law, with true-sign/Alternate Digit Inversion or true-sign/Inverted
Magnitude coding, respectively. Optionally, sign-magnitude coding may also be selected for proprietary
applications.
The Filter/Codec block also implements transmit and receive audio path gains in the analog domain. A
programmable gain, voice side-tone path is also included to provide proportional transmit speech feedback to the
handset receiver. This side tone path feature is disabled by default. Figure 3 depicts the nominal half-channel and
side-tone gains for the MT91L60/61.
In the event of PWRST, the MT91L60/61 defaults such that the side-tone path is off, all programmable gains are set
to 0dB and ITU-T µ-Law is selected. Further, the digital port is set to SSI mode operation at 2048 kb/s and the FDI
and driver sections are powered up. (See Microport section.)
The internal architecture is fully differential to provide the best possible noise rejection as well as to allow a wide
dynamic range from a single 3 volt supply design. This fully differential architecture is continued into the Transducer
Interface section to provide full chip realization of these capabilities for the handset functions.
A reference voltage (VRef), for the conversion requirements of the Codec section, and a bias voltage (VBias), for
biasing the internal analog sections, are both generated on-chip. VBias is also brought to an external pin so that it
may be used for biasing external gain setting amplifiers. A 0.1µF capacitor must be connected from VBias to analog
ground at all times. Although VRef may only be used internally, a 0.1µF capacitor must be connected from VRef to
ground. The analog ground reference point for these two capacitors must be physically the same point. To facilitate
this the VRef and VBias pins are situated on adjacent pins.
The transmit filter is designed to meet ITU-T G.714 specifications. The nominal gain for this filter is 0 dB (gain
control = 0 dB). Gain control allows the output signal to be increased up to 7 dB. An anti-aliasing filter is included.
This is a second order lowpass implementation with a corner frequency at 25 kHz.
The receive filter is designed to meet ITU-T G.714 specifications. The nominal gain for this filter is 0 dB (gain control
= 0 dB). Gain control allows the output signal to be attenuated up to 7 dB. Filter response is peaked to compensate
for the sinx/x attenuation caused by the 8 kHz sampling rate.
Side-tone is derived from the input of the Tx filter and is not subject to the gain control of the Tx filter section. Side-
tone is summed into the receive handset transducer driver path after the Rx filter gain control section so that Rx
gain adjustment will not affect side-tone levels. The side-tone path may be enabled/disabled with the gain control
bits located in Gain Control Register 2 (address 01h).
Transmit and receive filter gains are controlled by the TxFG0-TxFG2 and RxFG0-RxFG2 control bits, respectively.
These are located in Gain Control Register 1 (address 00h). Transmit filter gain is adjustable from 0dB to +7dB and
receive filter gain from 0dB to -7dB, both in 1dB increments.
Side-tone filter gain is controlled by the STG0-STG2 control bits located in Gain Control Register 2 (address 01h).
Side-tone gain is adjustable from
-9.96 dB to +9.96 dB in 3.32 dB increments.
Companding law selection for the Filter/Codec is provided by the A/µ companding control bit while the coding
scheme is controlled by the Smag/ITU-T control bit. The A/µ control bit is logically OR’ed with the A/µ pin providing
access in both controller and controllerless modes. Both A/µ and Smag/ITU-T reside in Control Register 2 (address
04h). Table 1 illustrates these choices.
5
Zarlink Semiconductor Inc.
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