MT9171/72
Data Sheet
with data rates up to 160 kbit/s. Both devices function identically but with the DSIC having a shorter maximum loop
reach specification. The generic "DNIC" will be used to reference both devices unless otherwise noted.
The MT9171/72 is fabricated in Zarlink’s ISO2-CMOS process.
22
21
20
19
18
17
16
15
14
13
12
1
2
3
4
5
6
7
8
LOUT
VBias
VRef
MS2
MS1
MS0
VDD
LIN
TEST
LOUT DIS
Precan
OSC1
OSC2
C4/TCK
F0o/RCK
DSTi/Di
DSTo/Do
•
NC
5
25
24
23
22
21
20
19
MS2
NC
MS1
MS0
RegC
LOUT DIS
Precan
OSC1
OSC2
NC
6
7
RegC
8
9
F0/CLD
CDSTi/CDi
CDSTo/CDo
VSS
10
11
9
10
11
F0/CLD
NC
C4/TCK
22 PIN PDIP
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
LOUT
VDD
LIN
TEST
LOUT DIS
Precan
OSC1
NC
VBias
VRef
MS2
MS1
MS0
RegC
NC
28 PIN PLCC
OSC2
9
C4/TCK
F0o/RCK
DSTi/Di
DSTo/Do
F0/CLD
CDSTi/CDi
CDSTo/CDo
VSS
10
11
12
24 PIN SSOP
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
22
24
28
1
2
3
1
2
3
2
3
4
LOUT
VBias
VRef
Line Out. Transmit Signal output (Analog). Referenced to VBias
Internal Bias Voltage output. Connect via 0.33 µF decoupling capacitor to VDD
Internal Reference Voltage output. Connect via 0.33 µF decoupling capacitor to
VDD
5,7, MS2-MS0 Mode Select inputs (Digital). The logic levels present on these pins select the
.
.
.
4,5, 4,5,
6
7
8
6
7
9
8
various operating modes for a particular application. See Table 1 for the
operating modes.
9
RegC
Regulator Control output (Digital). A 512 kHz clock used for switch mode power
supplies. Unused in MAS/MOD mode and should be left open circuit.
10
F0/CLD Frame Pulse/C-Channel Load (Digital). In DN mode a 244 ns wide negative
pulse input for the MASTER indicating the start of the active channel times of the
device. Output for the SLAVE indicating the start of the active channel times of
the device. Output in MOD mode providing a pulse indicating the start of the C-
channel.
2
Zarlink Semiconductor Inc.