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MT8972B PDF预览

MT8972B

更新时间: 2024-01-11 22:23:38
品牌 Logo 应用领域
MITEL 网络接口
页数 文件大小 规格书
20页 393K
描述
ISO2-CMOS ST-BUS⑩ FAMILY Digital Subscriber Interface Circuit Digital Network Interface Circuit

MT8972B 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:QFP包装说明:QCCJ, LDCC28,.5SQ
针数:28Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.81
Is Samacsys:N数据速率:160 Mbps
ISDN访问速率:BASICJESD-30 代码:S-PQCC-J28
JESD-609代码:e0长度:11.5062 mm
功能数量:1端子数量:28
最高工作温度:85 °C最低工作温度:-40 °C
最小输出高电压:2.4 V最大输出低电流:0.005 A
最大输出低电压:0.4 V封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC28,.5SQ
封装形状:SQUARE封装形式:FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
认证状态:Not Qualified参照点:S
座面最大高度:4.57 mm子类别:Digital Transmission Interfaces
最大压摆率:15 mA标称供电电压:5 V
表面贴装:YES技术:CMOS
电信集成电路类型:DIGITAL SLIC温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:11.5062 mm
Base Number Matches:1

MT8972B 数据手册

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MT8971B/72B  
In DIGITAL NETWORK (DN) mode, upon entering  
the DNIC from the DV and CD ports, the B-channel  
data, D-channel D0 (and D1 for 160 kbit/s), the HK  
bit of the C-channel (160kbit/s only) and a SYNC bit  
are combined in a serial format to be sent out on the  
line by the Transmit Interface (Figures 11, 12). The  
SYNC bit produces an alternating 1-0 pattern each  
frame in order for the remote end to extract the frame  
alignment from the line. It is possible for the remote  
end to lock on to a data bit pattern which simulates  
this alternating 1-0 pattern that is not the true SYNC.  
To decrease the probability of this happening the  
DNIC may be programmed to put the data through a  
prescrambler that scrambles the data according to a  
predetermined polynomial with respect to the SYNC  
bit. This greatly decreases the probability that the  
SYNC pattern can be reproduced by any data on the  
line. In order for the echo canceller to function  
correctly, a dedicated scrambler is used with a  
scrambling algorithm which is different for the SLV  
and MAS modes. These algorithms are calculated in  
such a way as to provide orthogonality between the  
near and far end data streams such that the  
correlation between the two signals is very low.  
For any two DNICs on a link, one must be in SLV  
mode with the other in MAS mode. The scrambled  
data is differentially encoded which serves to make  
the data on the line polarity-independent. It is then  
biphase encoded as shown in Figure 10. See “Line  
Interface” section for more details on the encoding.  
Before leaving the DNIC the differentially encoded  
biphase data is passed through a pulse-shaping  
bandpass transmit filter that filters out the high and  
low frequency components and conditions the signal  
for transmission on the line.  
The composite transmit and receive signal is  
received at LIN. On entering the DNIC this signal  
passes through a Precanceller which is a summing  
amplifier and lowpass filter that partially cancels the  
near-end signal and provides first order antialiasing  
for the received signal. Internal, partial cancellation  
of the near end signal may be disabled by holding  
F0  
C4  
C0 C1 C2 C3 C4 C5 C6 C7  
D0 D1 D2 D3 D4 D5 D6 D7  
C0  
C0  
CDSTo  
C0 C1 C2 C3 C4 C5 C6 C7  
D0 D1 D2 D3 D4 D5 D6 D7  
CDSTi  
F0o  
3.9 µsec  
62.5 µsec  
125 µsec  
Channel Time 0  
Channel Time 16  
Figure 7 - CD Port (Modes 2,6)  
CLD  
TCK  
CDi  
C6  
C6  
C7  
C7  
C0  
C0  
C1  
C1  
C2  
C2  
C3  
C3  
C4  
C4  
C5  
C5  
C6  
C6  
C7  
C7  
C0  
C0  
C1  
C1  
CDo  
Figure 8 - CD Port (Modes 1,5)  
9-112  

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