4Mb : 256K x 18, 128K x 32/36
FLOW-THROUGH SYNCBURST SRAM
3
READ TIMING
t
KC
CLK
t
t
KL
KH
t
t
ADSH
ADSS
ADSP#
ADSC#
t
t
ADSH
ADSS
Deselect Cycle
(Note 4)
t
t
AH
AS
A1
A2
ADDRESS
t
t
WH
WS
BWE#, GW#,
BWa#-BWd#
t
t
CEH
CES
CE#
(NOTE 2)
t
t
AAH
AAS
ADV#
OE#
ADV# suspends burst.
t
t
t
KQ
OEQ
OELZ
t
t
OEHZ
KQHZ
t
KQX
t
KQLZ
Q(A2)
Q(A2 + 1)
(NOTE 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A1)
Q
High-Z
t
KQ
Burst wraps around
to its initial state.
Single READ
BURST
READ
DON’T CARE
UNDEFINED
READ TIMING PARAMETERS
-6.8
-7.5
-8.5
-10
-6.8
-7.5
-8.5
-10
SYMBOL
MIN MAX MIN MAX MIN MAX MIN MAX UNITS
SYMBOL
MIN MAX MIN MAX MIN MAX MIN MAX UNITS
t
t
KC
7.5
8.8
10
15
ns
MHz
ns
AS
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
1.8
1.8
1.8
1.8
1.8
0.5
0.5
0.5
0.5
0.5
2.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
f
t
KF
133
6.8
113
7.5
100
8.5
66
10
ADSS
t
t
KH
2.5
2.5
2.5
2.5
3.0
3.0
4.0
4.0
AAS
t
t
KL
ns
WS
t
t
KQ
ns
CES
t
t
KQX
1.5
1.5
1.5
1.5
3.0
3.0
3.0
3.0
ns
AH
t
t
KQLZ
ns
ADSH
t
t
KQHZ
3.5
3.5
4.2
4.2
5.0
5.0
5.0
5.0
ns
AAH
t
t
OEQ
ns
WH
t
t
OELZ
0
0
0
0
ns
CEH
t
OEHZ
3.5
4.2
5.0
5.0
ns
NOTE: 1. Q(A2) refers to output from address A2. Q(A2 + 1) refers to output from the next internal burst address following A2.
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When
CE# is HIGH, CE2# is HIGH and CE2 is LOW.
3. Timing is shown assuming that the device was not enabled before entering into this sequence.
t
4. Outputs are disabled KQHZ after deselect.
4Mb: 256K x 18, 128K x 32/36 Flow-Through SyncBurst SRAM
MT58L256L18F1_D.p65 – Rev. 10/01
Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.
©2001, Micron Technology, Inc.
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