PRELIMINARY
4Mb : 256K x 18, 128K x 32/36
PIPELINED, SCD SYNCBURST SRAM
GENERAL DESCRIPTION (co n t in u e d )
pan sion (CE2, CE2#), burst con trol in puts (ADSC#,
ADSP#, ADV#), byte write en ables (BWx#) an d global
write (GW#).
Asyn ch ron ous in puts in clude th e output en able
(OE#), clock (CLK) an d sn ooze en able (ZZ). Th ere is also
a burst m ode in put (MODE) th at selects between in ter-
leaved an d lin ear burst m odes. Th e data-out (Q), en -
abled by OE#, is also asyn ch ron ous. WRITE cycles can
be from on e to two bytes wide (x18) or from on e to four
bytes wide (x32/x36), as con trolled by th e write con trol
in puts.
an d DQPb. Durin g WRITE cycles on th e x32 an d x36
devices, BWa# con trols DQa’s an d DQPa; BWb# con -
trols DQb’s an d DQPb; BWc# con trols DQc’s an d DQPc;
BWd# con trols DQd’s an d DQPd. GW# LOW causes all
bytes to be written . Parity bits are on ly available on th e
x18 an d x36 version s.
Th is device in corporates a sin gle-cycle deselect fea-
ture durin g READ cycles. If th e device is im m ediately
deselected after a READ cycle, th e output bus goes to a
t
High -Z state KQHZ n an osecon ds after th e risin g edge
of clock.
Burst operation can be in itiated with eith er address
status processor (ADSP#) or address status con troller
(ADSC#) in puts. Subsequen t burst addresses can be
in tern ally gen erated as con trolled by th e burst advan ce
in put (ADV#).
Address an d write con trol are registered on -ch ip to
sim plify WRITE cycles. Th is allows self-tim ed WRITE
cycles. In dividual byte en ables allow in dividual bytes
to be written . Durin g WRITE cycles on th e x18 device,
BWa# con trols DQa’s an d DQPa; BWb# con trols DQb’s
Micron ’s 4Mb Syn cBurst SRAMs operate from a
+3.3V VDD power supply, an d all in puts an d outputs are
TTL-com patible. Users can ch oose eith er a 3.3V or 2.5V
I/O version . Th e device is ideally suited for Pen tium an d
PowerPC pipelin ed system s an d system s th at ben efit
from a very wide, h igh -speed data bus. Th e device is also
ideal in gen eric 16-, 18-, 32-, 36-, 64- an d 72-bit-wide
application s.
Please refer to Micron ’s Web site (www.m icron .com /
m ti/m sp/h tm l/sram prod.h tm l) for th e latest data sh eet.
TQFP PIN ASSIGNMENT TABLE
PIN #
1
2
3
4
5
6
7
8
x18
NC
NC
NC
x32/x36
NC/DQPc*
DQc
PIN #
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
x18
x32/x36
VSS
VDDQ
DQd
DQd
NC/DQPd*
MODE
PIN #
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
x18
NC
NC
NC
x32/x36
NC/DQPa*
DQa
PIN #
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
x18
x32/x36
VSS
VDDQ
DQb
DQb
NC/DQPb*
SA
SA
ADV#
ADSP#
ADSC#
OE#
BWE#
GW#
CLK
DQc
NC
NC
NC
DQa
NC
NC
SA
VDDQ
VSS
VDDQ
VSS
NC
NC
DQb
DQb
DQc
DQc
DQc
DQc
NC
NC
DQa
DQa
SA
SA
SA
DQa
DQa
VSS
VDDQ
DQa
DQa
ZZ
VDD
NC
VSS
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VSS
VDDQ
SA
SA1
SA0
DNU
DNU
VSS
VDD
NF**
NF**
SA
DQb
DQb
DQc
DQc
VDD
VDD
NC
VSS
VDD
VSS
CE2#
BWa#
BWb#
DQb
DQb
DQd
DQd
DQa
DQa
DQb
DQb
VDDQ
VSS
SA
SA
SA
SA
SA
SA
VDDQ
VSS
NC
NC
BWc#
BWd#
DQb
DQb
DQPb
NC
DQd
DQd
DQd
DQd
DQa
DQa
DQPa
NC
DQb
DQb
DQb
DQb
CE2
CE#
SA
SA
*No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version.
**Pins 43 and 42 are reserved for address expansion, 8Mb and 16Mb respectively.
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L256L18P1.p65 – Rev. 3/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
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