Datasheet > MT58L128V36F1B-6.8IT

MT58L128V36F1B-6.8IT

更新时间： 2023-08-15 00:00:00

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
31页	628K
描述
Standard SRAM, 128KX36, 6.8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-028BHA, BGA-119

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数据手册

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MT58L128V36F1B-6.8IT 数据手册

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PRELIMINARY

4Mb: 256K x 18, 128K x 32/36

FLOW-THROUGH SYNCBURST SRAM

WRITE TIMING

CLK

ADSH

ADSS

ADSP#

ADSC# extends burst.

ADSH

ADSS

ADSH

ADSS

ADSC#

ADDRESS

BYTE WRITE signals are

ignored when ADSP# is LOW.

BWE#,

BWa#-BWd#

(NOTE 5)

GW#

CEH

CES

CE#

(NOTE 2)

AAS

AAH

ADV#

OE#

ADV# suspends burst.

(NOTE 4)

(NOTE 3)

D(A2)

D(A2 + 1)

(NOTE 1)

D(A2 + 1)

D(A2 + 2)

D(A2 + 3)

D(A3)

D(A3 + 1)

D(A3 + 2)

D(A1)

High-Z

OEHZ

BURST READ

Single WRITE

BURST WRITE

Extended BURST WRITE

DON’T CARE

WRITE TIMING PARAMETERS

-6.8

-7.5

-8.5

-10

-6.8

-7.5

-8.5

-10

SYMBOL

MIN MAX MIN MAX MIN MAX MIN MAX UNITS

SYMBOL

MIN MAX MIN MAX MIN MAX MIN MAX UNITS

7.5

8.8

MHz

1.5

0.5

1.5

0.5

1.8

0.5

2.0

0.5

133

3.5

113

4.2

100

5.0

CES

2.5

3.0

4.0

ADSH

OEHZ

5.0

AAH

1.5

1.8

2.0

ADSS

AAS

CEH

NOTE: 1. D(A2) refers to output from address A2. D(A2 + 1) refers to output from the next internal burst address following A2.

2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When

CE# is HIGH, CE2# is HIGH and CE2 is LOW.

3. OE# must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/

output data contention for the time period prior to the byte write enable inputs being sampled.

4. ADV# must be HIGH to permit a WRITE to the loaded address.

5. Full-width WRITE can be initiated by GW# LOW; or GW# HIGH and BWE#, BWa# and BWb# LOW for x18 device; or

GW# HIGH and BWE#, BWa#-BWd# LOW for x32 and x36 devices.

4Mb: 256K x 18, 128K x 32/36 Flow-Through SyncBurst SRAM

MT58L256L18F1_C.p65 – Rev. 6/01

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

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