Datasheet > MT58L128L18PF-5IT

MT58L128L18PF-5IT

更新时间： 2024-02-12 22:34:39

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器内存集成电路
页数	文件大小	规格书
25页	460K
描述
Standard SRAM, 128KX18, 3.5ns, CMOS, PBGA165, FBGA-165

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技术参数
数据手册

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MT58L128L18PF-5IT 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	TBGA,	针数：	165
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.58
最长访问时间：	3.5 ns	JESD-30 代码：	R-PBGA-B165
JESD-609代码：	e0	长度：	15 mm
内存密度：	2359296 bit	内存集成电路类型：	STANDARD SRAM
内存宽度：	18	湿度敏感等级：	3
功能数量：	1	端子数量：	165
字数：	131072 words	字数代码：	128000
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	128KX18
封装主体材料：	PLASTIC/EPOXY	封装代码：	TBGA
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, THIN PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	220
认证状态：	Not Qualified	座面最大高度：	1.2 mm
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	TIN LEAD	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	13 mm
Base Number Matches：	1

MT58L128L18PF-5IT 数据手册

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2Mb : 128K x 18, 64K x 32/36

PIPELINED, SCD SYNCBURST SRAM

TQFP PIN DESCRIPTIONS

x18

x32/x36

SYMBOL TYPE

DESCRIPTION

SA0

SA1

Input Synchronous Address Inputs: These inputs are registered and must

meet the setup and hold times around the rising edge of CLK.

32-35, 44-49, 32-35, 44-49,

80-82, 99,

100

81, 82, 99,

100

–

BWa#

BWb#

BWc#

BWd#

Input Synchronous Byte Write Enables: These active LOW inputs allow

individual bytes to be written and must meet the setup and hold

times around the rising edge of CLK. A byte write enable is LOW

for a WRITE cycle and HIGH for a READ cycle. For the x18 version,

BWa# controls DQa pins and DQPa; BWb# controls DQb pins and

DQPb. For the x32 and x36 versions, BWa# controls DQa pins and

DQPa; BWb# controls DQb pins and DQPb; BWc# controls DQc pins

and DQPc; BWd# controls DQd pins and DQPd. Parity is only

available on the x18 and x36 versions.

–

BWE#

GW#

CLK

Input Byte Write Enable: This active LOW input permits BYTE WRITE

operations and must meet the setup and hold times around the

rising edge of CLK.

Input Global Write: This active LOW input allows a full 18-, 32- or 36-bit

WRITE to occur independent of the BWE# and BWx# lines and must

meet the setup and hold times around the rising edge of CLK.

Input Clock: This signal registers the address, data, chip enable, byte write

enables, and burst control inputs on its rising edge. All synchronous

inputs must meet setup and hold times around the clock’s rising

edge.

CE#

CE2#

CE2

Input Synchronous Chip Enable: This active LOW input is used to enable

the device and conditions the internal use of ADSP#. CE# is sampled

only when a new external address is loaded.

Input Synchronous Chip Enable: This active LOW input is used to enable

the device and is sampled only when a new external address is

loaded.

Input Synchronous Chip Enable: This active HIGH input is used to enable

the device and is sampled only when a new external address is

loaded.

OE#

Input Output Enable: Thisactive LOW, asynchronous input enables the

data I/O output drivers.

ADV#

Input Synchronous Address Advance: This active LOW input is used to

advance the internal burst counter, controlling burst access after the

external address is loaded. A HIGH on this pin effectively causes wait

states to be generated (no address advance). To ensure use of

correct address during a WRITE cycle, ADV# must be HIGH at the

rising edge of the first clock after an ADSP# cycle is initiated.

ADSP#

Input SynchronousAddressStatusProcessor:ThisactiveLOWinput

interrupts any ongoing burst, causing a new external address to be

registered. A READ is performed using the new address,

independent of the byte write enables and ADSC#, but dependent

upon CE#, CE2 and CE2#. ADSP# is ignored if CE# is HIGH. Power-

down state is entered if CE2 is LOW or CE2# is HIGH.

2Mb:128Kx18, 64Kx32/36Pipelined, SCDSyncBurstSRAM

MT58L128L18P_2.p65 – Rev. 3/00

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

1 2 3 456 7 8...25

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与MT58L128L18PF-5IT相关器件

型号	品牌	获取价格	描述	数据表
MT58L128L18PF-6	CYPRESS	获取价格	Standard SRAM, 128KX18, 3.5ns, CMOS, PBGA165, FBGA-165
MT58L128L18PF-6IT	CYPRESS	获取价格	Standard SRAM, 128KX18, 3.5ns, CMOS, PBGA165, FBGA-165
MT58L128L18PF-7.5	CYPRESS	获取价格	Standard SRAM, 128KX18, 4ns, CMOS, PBGA165, FBGA-165
MT58L128L18PF-7.5IT	CYPRESS	获取价格	Standard SRAM, 128KX18, 4ns, CMOS, PBGA165, FBGA-165
MT58L128L18PT-10	CYPRESS	获取价格	Cache SRAM, 128KX18, 5ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100
MT58L128L18PT-10IT	CYPRESS	获取价格	Cache SRAM, 128KX18, 5ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100
MT58L128L18PT-10T	CYPRESS	获取价格	Cache SRAM, 128KX18, 5ns, CMOS, PQFP100, PLASTIC, MS-026, TQFP-100
MT58L128L18PT-5	CYPRESS	获取价格	Cache SRAM, 128KX18, 3.5ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100
MT58L128L18PT-5IT	CYPRESS	获取价格	Cache SRAM, 128KX18, 3.5ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100
MT58L128L18PT-6IT	CYPRESS	获取价格	Cache SRAM, 128KX18, 3.5ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100

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