18Mb: 1 MEG x 18, 512K x 32/36
FLOW-THROUGH ZBT SRAM
Table 1:
TQFP Pin Descriptions
SYMBOL
TYPE
DESCRIPTION
ADV/LD#
Input
Synchronous Address Advance/Load: When HIGH, this input is used to advance the internal
burst counter, controlling burst access after the external address is loaded. When ADV/LD# is
HIGH, R/W# is ignored. A LOW on ADV/LD# clocks a new address at the CLK rising edge.
BWa#
BWb#
BWc#
BWd#
Input
Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to be
written when a WRITE cycle is active and must meet the setup and hold times around the
rising edge of CLK. BWs need to be asserted on the same cycle as the address. BWs are
associated with addresses and apply to subsequent data. BWa# controls DQa pins; BWb#
controls DQb pins; BWc# controls DQc pins; BWd# controls DQd pins.
CE#
Input
Input
Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled
only when a new external address is loaded (ADV/LD# LOW).
CE2#
Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled
only when a new external address is loaded (ADV/LD# LOW). This input can be used for
memory depth expansion.
CE2
Input
Input
Synchronous Chip Enable: This active HIGH input is used to enable the device and is sampled
only when a new external address is loaded (ADV/LD# LOW). This input can be used for
memory depth expansion.
CKE#
Synchronous Clock Enable: This active LOW input permits CLK to propagate throughout the
device. When CKE is HIGH, the device ignores the CLK input and effectively internally
extends the previous CLK cycle. This input must meet setup and hold times around the rising
edge of CLK.
CLK
Input
Input
Clock: This signal registers the address, data, chip enables, byte write enables, and burst
control inputs on its rising edge. All synchronous inputs must meet setup and hold times
around the clock’s rising edge.
MODE (LBO#)
Mode: This input selects the burst sequence. A LOW on this pin selects linear burst. NC or
HIGH on this pin selects interleaved burst. Do not alter input state while device is operating.
LBO# is the JEDEC-standard term for MODE.
OE# (G#)
R/W#
Input
Input
Output Enable: This active LOW, asynchronous input enables the data I/O output drivers. G#
is the JEDEC-standard term for OE#.
Read/Write: This input determines the cycle type when ADV/LD# is LOW and is the only
means for determining READs and WRITEs. READ cycles may not be converted into WRITEs
(and vice versa) other than by loading a new address. A LOW on this pin permits BYTE WRITE
operations and must meet the setup and hold times around the rising edge of CLK. Full bus-
width WRITEs occur if all byte write enables are LOW.
SA0
SA1
SA
Input
Input
Synchronous Address Inputs: These inputs are registered and must meet the setup and hold
times around the rising edge of CLK. SA0 and SA1 are the two least significant bits (LSB) of
the address field and set the internal burst counter if burst is desired.
ZZ
Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-power
standby mode in which all data in the memory array is retained. When ZZ is active, all other
inputs are ignored. This pin has an internal pull-down and can be left unconnected.
DQa
DQb
DQc
DQd
Input/
Output
SRAM Data I/Os: Byte “a” is associated with DQa pins; byte “b” is associated with DQb pins;
byte “c” is associated with DQc pins; byte “d” is associated with DQd pins. Input data must
meet setup and hold times around the rising edge CLK.
NF/DQPa
NF/DQPb
NF/DQPc
NF/DQPd
NF
I/O
No Function/Parity Data I/Os: On the x32 version, these are No Function (NF). On the x18
version, byte “a” parity is DQPa; byte “b” parity is DQPb. On the x36 version, byte “a” parity
is DQPa; byte “b” parity is DQPb; byte “c” parity is DQPc; byte “d” parity is DQPd.
VDD
Supply
Supply
Power Supply: See DC Electrical Characteristics and Operating Conditions for range.
VDDQ
Isolated Output Buffer Supply: See DC Electrical Characteristics and Operating Conditions for
range.
VSS
Supply
Ground: GND.
18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM
MT55L1MY18F_16_D.fm – Rev. D, Pub. 2/03
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
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