MT42C4256 883C
256K x 4 VRAM
AUSTIN SEMICONDUCTOR, INC.
Limited Supply - Consult Factory
256K x 4 DRAM
VRAM
WITH 512 x 4 SAM
AVAILABLE AS MILITARY
SPECIFICATION
PIN ASSIGNMENT (Top View)
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SMD 5962-89497
MIL-STD-883
28-Pin DIP
(400 MIL)
28-Pin SOJ
28-Pin LCC
FEATURES
SC
SDQ1
SDQ2
TR/OE
DQ1
1
2
3
4
5
6
7
8
9
28 Vss
SC
SDQ1
SDQ2
TR/OE
DQ1
1
2
3
4
5
6
7
8
9
28 Vss
27 SDQ4
26 SDQ3
25 SE
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Industry standard pinout, timing and functions
High-performance, CMOS silicon-gate process
Single +5V ±10% power supply
Inputs and outputs are fully TTL compatible
Refresh modes: RAS-ONLY, CAS-BEFORE-RAS (CBR)
and HIDDEN
27 SDQ4
26 SDQ3
25 SE
24 DQ4
23 DQ3
22 DSF
21 CAS
20 QSF
24 DQ4
23 DQ3
22 DSF
21 CAS
20 QSF
19 A0
DQ2
DQ2
ME/WE
NC
ME/WE
NC
RAS
RAS
A0
A8 10
A6 11
A5 12
A4 13
Vcc 14
A8 10
A6 11
A5 12
A4 13
Vcc 14
19
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512-cycle refresh within 8ms
18 A1
18 A1
17 A2
16 A3
15 A7
Optional FAST PAGE MODE access cycles
Dual port organization: 256K x 4 DRAM port
512 x 4 SAM port
17 A2
16 A3
15 A7
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No refresh required for serial access memory
Low power: 15mW standby; 275mW active, typical
28-Pin FP
(F-12)
SPECIAL FUNCTIONS
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JEDEC Standard Function set
PERSISTENT MASKED WRITE
SPLIT READ TRANSFER
WRITE TRANSFER/ SERIAL INPUT
ALTERNATE WRITE TRANSFER
BLOCK WRITE
SC
SDQ1
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vss
SDQ4
SDQ3
SE
DQ4
DQ3
DSF
CAS
QSF
A0
SDQ2
TR/OE
DQ1
DQ2
ME/WE
NC
RAS
A8
A6
9
10
11
12
13
14
OPTIONS
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MARKING
Timing [DRAM, SAM (cycle/ access)]
A1
A2
A3
A7
A5
A4
Vcc
80ns, 30ns/ 25ns
100ns, 30ns/ 27ns
120ns, 35ns/ 35ns
- 8
-10
-12
•
Packages
Ceramic SOJ
DCJ No. 500
Ceramic DIP (400 mil)
Ceramic LCC
Ceramic Flat Pack
C
No. 109
EC No. 203
No. 302
The DRAM portion ofthe VRAM is functionally identical
to the MT4C4256 (256K x 4 DRAM). Four 512-bit data
registers make up the SAM portion of the VRAM. Data I/ O
and internal data transfer are accomplished using three
separate bidirectional data paths; the 4-bit random access
I/ O port, the four internal 512 bit wide paths between the
DRAM and the SAM, and the 4-bit serial I/ O port for the
SAM. The rest of the circuitry consists of the control, timing
and address decoding logic.
F
GENERAL DESCRIPTION
The MT42C4256 883C is a high-speed, dual port CMOS
dynamic random access memory or video RAM (VRAM)
containing 1,048,576 bits. These bits may be accessed by a
4-bit wide DRAM port or a 512 x 4-bit serial access memory
(SAM) port. Data may be transferred bidirectionally be-
tween the DRAM and the SAM.
Each port may be operated asynchronously and indepen-
dently of the other except when data is being transferred
MT42C4256 883C
REV. 3/97
DS000016
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
3-27