Datasheet > MT42L16M32D1HE-18 IT

MT42L16M32D1HE-18 IT

更新时间： 2024-11-21 15:19:19

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MT42L16M32D1

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Micron Confidential and Proprietary

134b: x32 Embedded LPDDR2 SDRAM

Features

Embedded LPDDR2 SDRAM

MT42L16M32D1

Options

Marking

Features

• Ultra low-voltage core and I/O power supplies

– V_DD2= 1.14–1.30V

– V_DDCA/V_DDQ= 1.14–1.30V

– V_DD1= 1.70–1.95V

• V_DD2: 1.2V

• Configuration

– 4 Meg x 32 x 4 banks

• Device type

16M32

– LPDDR2-S4, 1 die in package

• FBGA “green” package

– 134-ball FBGA

(10mm x 11.5mm)

• Timing – cycle time

– 1.875ns @ RL = 8

• Operating temperature range¹

– From –40°C to +85°C

• Revision

• Clock frequency range

– 533–10 MHz (data rate range: 1066–20 Mb/s/pin)

• Four-bit prefetch DDR architecture

• Eight internal banks for concurrent operation

• Multiplexed, double data rate, command/address

inputs; commands entered on every CK edge

• Bidirectional/differential data strobe per byte of

data (DQS/DQS#)

• Programmable READ and WRITE latencies (RL/WL)

• Programmable burst lengths: 4, 8, or 16

• Per-bank refresh for concurrent operation

• On-chip temperature sensor to control self refresh

rate (SR not supported >105°C)

-18

• Partial-array self refresh (PASR)

• Deep power-down mode (DPD)

• Selectable output drive strength (DS)

• Clock stop capability

• RoHS-compliant, “green” packaging

Table 1: Key Timing Parameters

Speed

Grade

Clock Rate

(MHz)

Data Rate

(Mb/s/pin)

-18

533

1066

Table 2: S4 Configuration Addressing

Architecture

16 Meg x 32

Die configuration

Row addressing

Column addressing

Number of die

4 Meg x 32 x 4 banks

8K (A[12:0])

512 (A[8:0])

Die per rank

Ranks per channel¹

1. A channel is a complete LPDRAM interface, including command/address and data pins.

Note:

CCM005-196791117-10298

u07m_it_lpddr2.pdf - Rev. B 07/2020 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

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