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MT41K1G4 PDF预览

MT41K1G4

更新时间: 2024-09-28 12:28:39
品牌 Logo 应用领域
镁光 - MICRON 动态存储器双倍数据速率
页数 文件大小 规格书
27页 553K
描述
4Gb: x4, x8, x16 1.35V DDR3L SDRAM

MT41K1G4 数据手册

 浏览型号MT41K1G4的Datasheet PDF文件第2页浏览型号MT41K1G4的Datasheet PDF文件第3页浏览型号MT41K1G4的Datasheet PDF文件第4页浏览型号MT41K1G4的Datasheet PDF文件第5页浏览型号MT41K1G4的Datasheet PDF文件第6页浏览型号MT41K1G4的Datasheet PDF文件第7页 
4Gb: x4, x8, x16 DDR3L SDRAM  
Description  
1.35V DDR3L SDRAM  
MT41K1G4 – 128 Meg x 4 x 8 banks  
MT41K512M8 – 64 Meg x 8 x 8 banks  
MT41K256M16 – 32 Meg x 16 x 8 banks  
• TC of 0°C to +95°C  
– 64ms, 8192-cycle refresh at 0°C to +85°C  
– 32ms at +85°C to +95°C  
• Self refresh temperature (SRT)  
• Automatic self refresh (ASR)  
• Write leveling  
Description  
DDR3L SDRAM (1.35V) is a low voltage version of the  
DDR3 SDRAM (1.5V).  
Features  
• VDD = VDDQ = 1.35V (1.283–1.45V)  
• Backward compatible to VDD = VDDQ = 1.5V ±0.075V  
– Supports DDR3L devices to be backward com-  
patible in 1.5V applications  
• Multipurpose register  
• Output driver calibration  
Options  
• Configuration  
– 1 Gig x 4  
– 512 Meg x 8  
Marking  
• Differential bidirectional data strobe  
• 8n-bit prefetch architecture  
• Differential clock inputs (CK, CK#)  
• 8 internal banks  
• Nominal and dynamic on-die termination (ODT)  
for data, strobe, and mask signals  
• Programmable CAS (READ) latency (CL)  
• Programmable posted CAS additive latency (AL)  
• Programmable CAS (WRITE) latency (CWL)  
• Fixed burst length (BL) of 8 and burst chop (BC) of 4  
(via the mode register set [MRS])  
1G4  
512M8  
256M16  
– 256 Meg x 16  
• FBGA package (Pb-free) – x4, x8  
– 78-ball (10.5mm x 12mm) Rev. D  
– 78-ball (9mm x 10.5mm) Rev. E, J  
• FBGA package (Pb-free) – x16  
– 96-ball (10mm x 14mm) Rev. D  
– 96-ball (9mm x 14mm) Rev. E  
• Timing – cycle time  
– 1.071ns @ CL = 13 (DDR3-1866)  
– 1.25ns @ CL = 11 (DDR3-1600)  
– 1.5ns @ CL = 9 (DDR3-1333)  
– 1.87ns @ CL = 7 (DDR3-1066)  
• Operating temperature  
– Commercial (0°C TC +95°C)  
– Industrial (–40°C TC +95°C)  
• Revision  
RA  
RH  
RE  
HA  
• Selectable BC4 or BL8 on-the-fly (OTF)  
• Self refresh mode  
-107  
-125  
-15E  
-187E  
None  
IT  
:D/:E/:J  
Table 1: Key Timing Parameters  
Speed Grade  
-1071, 2, 3  
-1251, 2  
Data Rate (MT/s)  
Target tRCD-tRP-CL  
13-13-13  
tRCD (ns)  
13.91  
13.75  
13.5  
tRP (ns)  
13.91  
13.75  
13.5  
CL (ns)  
13.91  
13.75  
13.5  
1866  
1600  
1333  
1066  
11-11-11  
-15E1  
9-9-9  
-187E  
7-7-7  
13.1  
13.1  
13.1  
1. Backward compatible to 1066, CL = 7 (-187E).  
2. Backward compatible to 1333, CL = 9 (-15E).  
3. Backward compatible to 1600, CL = 11 (-107).  
Notes:  
PDF: 09005aef84780270  
4Gb_DDR3L_SDRAM.pdf - Rev. H 4/13 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
1
© 2011 Micron Technology, Inc. All rights reserved.  
Products and specifications discussed herein are subject to change by Micron without notice.  

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