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MSM7652 PDF预览

MSM7652

更新时间: 2022-12-12 11:17:31
品牌 Logo 应用领域
冲电气 - OKI 编码器
页数 文件大小 规格书
36页 306K
描述
NTSC/PAL Digital Video Encoder

MSM7652 数据手册

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¡ Semiconductor  
MSM7652  
PIN DESCRIPTIONS (1/2)  
Pin  
1
I/O  
Symbol  
DVDD  
MS  
Description  
3.3 V digital power supply  
2
I
I/O  
I
Selects between Master and Slave at 27 MHz or 13.5 MHz YCbCr operation. Pulled down  
I2C interface data bus  
3
SDA  
4
SCL  
I2C interface clock bus  
I2C-bus Slave address setting pin ("0" : 1000100 / "1" : 1000110).  
5
I
ADRS  
Pulled down  
6
7
I
I
RESET_L  
MODE  
OLC  
System reset signal. Negative porality  
Broadcasting mode select pin. "0" : NTSC/"1" : PAL. Pulled down  
Transparent control signal. "1" indicates overlay signal. Normally fixed to "0".  
Overlay text color (Red component). Normally fixed to "0".  
Overlay text color (Green component). Normally fixed to "0".  
Overlay text color (Blue component). Normally fixed to "0".  
13.5 MHz divided clock output signal  
8
I
9
I
OLR  
10  
11  
12  
I
OLG  
I
OLB  
O
CLKX1O  
Video output signal format select pin. "0" : Y/C & Composite signal,  
"1" : Y/B-Y/R-Y (component) signal. Pulled down  
3.3 V digital power supply  
13  
I
OUTSEL  
14  
15  
DVDD  
DGND  
Digital GND  
Vertical sync signal input/output pin (ITU656: O, YCbCr: I/O)  
Negative polarity  
16  
17  
18  
I/O  
I/O  
I
VSYNC_L  
HSYNC_L  
BLANK_L  
Horizontal signal input/output pin (ITU656 : O, YCbCr: I/O)  
Negative polarity  
Composite blank signal. Negative polarity. See the description on page 15  
for the operating requirement.  
MSB 2 bits of 8-bit digital image data input pins (for ITU656 and  
YCbCr 27 MHz). Level conforms to ITU-601.  
19, 20  
21  
I
I
YD7 to YD6 MSB 2 bits of 8-bit digital image luminance signal input pins (for YCbCr).  
Level conforms to ITU-601.  
YD7 is MSB.  
NC  
Not connected  
LSB 6 bits of 8-bit digital image data input pins (for ITU656 and  
YCbCr 27 MHz). Level conforms to ITU-601.  
22 to 27  
YD5 to YD0 LSB 6 bits of 8-bit digital image luminance signal input pins (for YCbCr).  
Level conforms to ITU-601.  
YD0 is LSB.  
28  
29  
30  
DGND  
DVDD  
Digital GND  
3.3 V digital power supply  
I
I/O  
I
CLKX2  
Clock input pin (27 MHz)  
8bit digital image chrominance signal data input pins (13.5 MHz mode).  
Level conforms to ITU-601. Fixed to "0" for ITU Rec. 656, 27 MHz-YCbCr mode.  
Operation mode select pin. "0" : 27 MHz mode / "1" : 13.5 MHz mode.  
31 to 38  
39  
CD7 to CD0  
CLKSEL  
5

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