Datasheet > MSM548263

MSM548263

更新时间： 2022-12-13 04:56:09

品牌	Logo	应用领域
冲电气 - OKI		动态存储器
页数	文件大小	规格书
40页	387K
描述
262,144-Word x 8-Bit Multiport DRAM

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MSM548263 数据手册

¡ Semiconductor

MSM548263

Notes: 1. Exposure beyond the "Absolute Maximum Ratings" may cause permanent damage

to the device.

2. All voltages are referenced to V .

3. These parameters depend on the cycle rate.

4. Theseparametersdependonoutputloading.Specifiedvaluesareobtainedwiththe

output open.

5. An initial pause of 200 ms is required after power up followed by any 8 RAS cycles

(TRG = "high") and any 8 SC cycles before proper device operation is achieved.

In the case of using an internal refresh counter, a minimum of 8 CAS before RAS

cycles instead of 8 RAS cycles are required.

6. AC measurements assume t = 5 ns.

7. V (Min.)andV (Max.)arereferencelevelsformeasuringtimingofinputsignals.

Also, transition times are measured between V and V .

8. RAM port outputs are measured with a load equivalent to 1 TTL load and 50 pF.

DOUT reference levels : V /V = 2.0 V/0.8 V.

9. SAM port outputs are measured with a load equivalent to 1 TTL load and 30 pF.

DOUT reference levels : V /V = 2.0 V/0.8 V.

10. t

(Max.), t

(Max.) and t

(Max.) define the time at which the

OFF

OEZ

SDZ

SEZ

outputsachievetheopencircuitcondition, andarenotreferencedtooutputvoltage

levels. This parameter is sampled and not 100% tested.

11. Either t

or t

must be satisfied for a read cycle.

RCH

RRH

12. These parameters are referenced to CAS leading edge of early write cycles, and to

WE leading edge in TRG controlled write cycles and read modify write cycles.

13. t

, t

and t

are not restrictive operating parameters.

AWD

WCS RWD CWD

They are included in the data sheet as electrical characteristics only.

If t ≥ t (Min.), the cycle is an early write cycle, and the data out pin will

WCS

remain open circuit throughout the entire cycle; If t

≥t

(Min.), t

≥t

RWD RWD

CWD CWD

(Min.) and t

≥ t

(Min.), the cycle is a read modify write cycle, and the data

AWD AWD

out will contain data read from the selected cell; If neither of the above sets of

conditions are satisfied, the condition of the data out is indeterminate.

14. Operation within the t

(Max.) limit ensures that t

(Max.) can be met.

RCD

RAC

(Max.)isspecifiedasareferencepointonly:Ift

(Max.) limit, then access time is controlled by t

isgreaterthanthespecified

RCD

CAC

15. Operation within the t

(Max.) limit ensures that t

(Max.) can be met. t

RAD

RAC

RAD

(Max.)isspecifiedasareferencepointonly:Ift

isgreaterthanthespecifiedt

RAD

(Max.) limit, then access time is controlled by t

16. Input levels at the AC testing are 3.0 V/0 V.

17. Address (A0 - A8) may be changed two times or less while RAS = V .

18. Address (A0 - A8) may be changed once or less while CAS = V and RAS = V .

19. This is guaranteed by design. (t

= t

- output transition time)

SOH COH

SCA CAC

This parameter is not 100% tested.

9/40

1...6 7 8910 11 12...40

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与MSM548263相关器件

型号	品牌	描述	获取价格	数据表
MSM548263-60JS	OKI	Video DRAM, 256KX8, 60ns, CMOS, PDSO40, 0.400 INCH, 1.27 MM PITCH, PLASTIC, SOJ-40	获取价格
MSM548263-60TS-K	OKI	Video DRAM, 256KX8, 60ns, CMOS, PDSO40, 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-44/40	获取价格
MSM548263-70JS	OKI	Video DRAM, 256KX8, 70ns, CMOS, PDSO40, 0.400 INCH, 1.27 MM PITCH, PLASTIC, SOJ-40	获取价格
MSM548263-70TS-K	OKI	Video DRAM, 256KX8, 70ns, CMOS, PDSO40, 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-44/40	获取价格
MSM548263-80TS-K	OKI	Video DRAM, 256KX8, 80ns, CMOS, PDSO40, 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-44/40	获取价格
MSM548331	OKI	222,720-Word x 12-Bit Field Memory	获取价格

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