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MSM548263 PDF预览

MSM548263

更新时间: 2022-12-13 04:56:09
品牌 Logo 应用领域
冲电气 - OKI 动态存储器
页数 文件大小 规格书
40页 387K
描述
262,144-Word x 8-Bit Multiport DRAM

MSM548263 数据手册

 浏览型号MSM548263的Datasheet PDF文件第34页浏览型号MSM548263的Datasheet PDF文件第35页浏览型号MSM548263的Datasheet PDF文件第36页浏览型号MSM548263的Datasheet PDF文件第38页浏览型号MSM548263的Datasheet PDF文件第39页浏览型号MSM548263的Datasheet PDF文件第40页 
¡ Semiconductor  
MSM548263  
Masked Split Write Transfer: RAS falling edge --- CAS = DSF = "H", TRG = WE = "L"  
Split write transfer consists of loading 256 words by 8 bits of data from the non-active split SAM  
register into a selected row of the corresponding split RAM. Serial data can be shifted into the  
other half of the split SAM register simultaneously. During split write transfer operation, the  
RAM port input clocks do not have to be synchronized with the serial clock SC, thus allowing  
for real time transfer. This operation is the same as a mask write operation in RAM, so new and  
persistent mode can be supported.  
A split write transfer can be performed after a delay of t  
from the change of state of the QSF  
STS  
output is satisfied.  
A masked write transfer operation must precede split write transfer. The purpose is to switch the  
SAM port from output mode to input mode, and to set the initial TAP location prior to split write  
transfer operations.  
Programmable SAM Stops in Split Transfer Cycle  
The MSM548263 has a boundary split register operation using programmable stops. If a CBRS  
cycle has been performed, the split transfer cycle performs the boundary operation.  
Figure 2 shows an example of a boundary split register (4 stop points). The stop points define a  
SAM location at which the access will change from one half of the SAM to the other half (at the  
TAP address).  
Lower SAM  
TAP3  
Upper SAM  
TAP2  
TAP1  
0
255  
256  
511  
S.T. (TAP2)  
S.T. (TAP3)  
Figure 2. Example of Boundary Split Register  
37/40  

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