Datasheet > MS6266SSTR

MS6266SSTR

更新时间： 2024-01-11 12:09:52

品牌	Logo	应用领域
茂升 - MOSA		控制器
页数	文件大小	规格书
11页	620K
描述
6-Channel Volume Controller Gain and Attenuation 16-79dB Low voltage, High Channel Separation

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技术参数
数据手册

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MS6266SSTR 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.84
Base Number Matches：	1

MS6266SSTR 数据手册

MS6266

MOSA

6-Channel Electronic Volume Controller

I²C BUS DESCRIPTION

Start and stop conditions

A start condition is activated when the SCL is set to HIGH and SDA shifts from HIGH to LOW state. The stop

condition is activated when SCL is set to HIGH and SDA shifts from LOW to HIGH state. Please refer to the timing

diagram below.

SCL

SDA

Start

Stop

SCL : Serial Clock Line, SDA : Serial Data Line

Data validity

A data on the SDA line is considered valid and stable only when the SCL signal is in HIGH state. The HIGH and

LOW states of the SDA line can only change when the SCL signal is LOW. Please refer to the figure below.

SDA

SCL

Data line

stable,

Data

change

Data valid allowed

Byte format

Every byte transmitted to the SDA line consists of 8 bits. Each byte must be followed by an acknowledge bit.

The MSB is transmitted first.

Acknowledge

During the Acknowledge clock pulse, the master (up) put a resistive HIGH level on the SDA line. The peripheral

(audio processor) that acknowledges has to pull-down (LOW) the SDA line during the Acknowledge clock pulse so that

the SDA line is in a stable LOW state during this clock pulse. Please refer to the diagram below.

SCL

SDA

MSB

Acknowledge

Start

The audio processor that has been addressed has to generate an Acknowledge after receiving each byte, otherwise,

the SDA line will remain at the HIGH level during the ninth (9^th) clock pulse. In this case, the master transmitter can

generate the STOP information in order to abort the transfer.

REV1

www.mosanalog.com.tw

1 2 3 456 7 8...11

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