Datasheet > MS6258SSTR

MS6258SSTR

更新时间： 2024-01-31 05:37:43

品牌	Logo	应用领域
茂升 - MOSA		/
页数	文件大小	规格书
12页	673K
描述
Gain and Attenuation Volume Controller IC 4 Sets of Stereo Input, Low voltage Gain and Attenuation 15~-79dB

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数据手册

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MS6258SSTR 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.84
Base Number Matches：	1

MS6258SSTR 数据手册

MS6258

MOSA

Gain And Attenuation Volume Controller IC

Acknowledge

During the Acknowledge clock pulse, the master (up) put a resistive HIGH level on the SDA line. The peripheral

(audio processor) that acknowledges has to pull-down (LOW) the SDA line during the Acknowledge clock pulse so that

the SDA line is in a stable LOW state during this clock pulse. Please refer to the diagram below.

SCL

SDA

MSB

Acknowledge

Start

The audio processor that has been addressed has to generate an Acknowledge after receiving each byte, otherwise,

the SDA line will remain at the HIGH level during the ninth (9^th) clock pulse. In this case, the master transmitter can

generate the STOP information in order to abort the transfer.

Timing of SDA and SCL bus lines

SDA

tSU;DAT

tLOW

tBUF

tHD;STA

SCL

tHD;STA

tSU;STA

tSU;STO

tHIGH

tHD;DAT

Standard mode

Symbol

Min

Max

Unit

Parameter

f_SCL

SCL clock frequency

Hold time (repeated) START condition.

After this period, the first clock pulse is generated

100

kHz

t_HD:STA

4.0

t_LOW

LOW period of the SCL clock

4.7

4.0

4.7

t_HIGH

t_SU:STA

HIGH period of the SCL clock

Set-up time for a repeated START condition

Data hold time:

t_HD:DAT

3.45

For I²C-bus devices

t_SU:DAT

t_r

Data-set-up time

250

1000

300

Rise time of both SDA and SCL signals

Fall time of both SDA and SCL signals

Set-up time for STOP condition

t_f

t_SU:STO

t_BUF

C_b

4.0

4.7

Bus free time between a STOP and START condition

Capacitive load for each bus line

400

Noise margin at the LOW level for each connected device (including

hysteresis)

V_nL

V_nH

0.1V_DD

0.2V_DD

Noise margin at the HIGH level for each connected device (including

hysteresis)

REV 1

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