Introduction
ADC
BAM
CAN
CMU
CRC
CTU
– Analog-to-digital converter
– Boot assist module
– Controller area network controller
– Clock monitoring unit
– Cyclic redundancy check unit
– Cross Triggering Unit
– Error correction code
– Error correction status module
– Enhanced direct memory access controller
– Fault collection and control unit
– Frequency modulated phase locked loop
– Interrupt controller
PMU
PWM
RC
– Power management unit
– Pulse width modulator module
– Redundancy checker
– Real time clock
– Semaphore unit
– System integration unit lite
– Serial peripherals interface controller
– System status and configuration module
– System timer module
– Sine wave generator
– Software watchdog timer
– Temperature sensor
RTC
SEMA4
SIUL
SPI
SSCM
STM
SWG
SWT
TSENS
ECC
ECSM
eDMA
FCCU
FMPLL
INTC
IRCOSC – Internal RC oscillator
UART/LIN – Universal asynchronous receiver/transmitter/
JTAG
MC
– Joint Test Action Group interface
– Mode entry, clock, reset, & power
local interconnect network
– Wakeup unit
– Crystal oscillator
WKPU
XOSC
PBRIDGE – Peripheral I/O bridge
PIT – Periodic interrupt timer
Figure 2. PXS20 block diagram (continued)
1.5
Feature details
1.5.1
High-Performance e200z4d Core
®
The e200z4d Power Architecture core provides the following features:
•
•
2 independent execution units, both supporting fixed-point and floating-point operations
®
Dual issue 32-bit Power Architecture technology compliant
— 5-stage pipeline (IF, DEC, EX1, EX2, WB)
— In-order execution and instruction retirement
®
•
Full support for Power Architecture instruction set and Variable Length Encoding (VLE)
— Mix of classic 32-bit and 16-bit instruction allowed
— Optimization of code size possible
Thirty-two 64-bit general purpose registers (GPRs)
Harvard bus (32-bit address, 64-bit data)
— I-Bus interface capable of one outstanding transaction plus one piped with no wait-on-data return
— D-Bus interface capable of two transactions outstanding to fill AHB pipe
I-cache and I-cache controller
•
•
•
— 4 KB, 256-bit cache line (programmable for 2- or 4-way)
No data cache
•
•
•
•
•
•
•
16-entry MMU
8-entry branch table buffer
Branch look-ahead instruction buffer to accelerate branching
Dedicated branch address calculator
3 cycles worst case for missed branch
Load/store unit
— Fully pipelined
— Single-cycle load latency
— Big- and little-endian modes supported
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
7
Preliminary—Subject to Change Without Notice
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