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MPC862D

更新时间： 2024-02-12 15:01:39

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		/
页数	文件大小	规格书
88页	1098K
描述
Hardware Specifications

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中文翻译

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技术参数
数据手册

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MPC862D 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.84
Base Number Matches：	1

MPC862D 数据手册

Freescale Semiconductor, Inc.

Features

— Optional statistical cell counters per PHY

— UTOPIA level 2 compliant interface with added FIFO buffering to reduce the total cell

transmission time. (The earlier UTOPIA level 1 speciﬁcation is also supported.)

— Multi-PHY support on the MPC857T

— Four PHY support on the MPC857DSL

— Parameter RAM for both SPI and I C can be relocated without RAM-based microcode

— Supports full-duplex UTOPIA both master (ATM side) and slave (PHY side) operation using a

“split” bus

— AAL2/VBR functionality is ROM-resident

Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)

32 address lines

•

Memory controller (eight banks)

— Contains complete dynamic RAM (DRAM) controller

— Each bank can be a chip select or RAS to support a DRAM bank

— Up to 30 wait states programmable per memory bank

— Glueless interface to Page mode/EDO/SDRAM, SRAM, EPROMs, ﬂash EPROMs, and other

memory devices.

— DRAM controller programmable to support most size and speed memory interfaces

— Four CAS lines, four WE lines, one OE line

— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)

— Variable block sizes (32 Kbyte–256 Mbyte)

— Selectable write protection

— On-chip bus arbitration logic

•

General-purpose timers

— Four 16-bit timers cascadable to be two 32-bit timers

— Gate mode can enable/disable counting

— Interrupt can be masked on reference match and event capture

Fast Ethernet controller (FEC)

•

— Simultaneous MII (10/100Base-T) and UTOPIA operation when using the UTOPIA

multiplexed bus.

System integration unit (SIU)

— Bus monitor

— Software watchdog

— Periodic interrupt timer (PIT)

— Low-power stop mode

— Clock synthesizer

— Decrementer, time base, and real-time clock (RTC) from the PowerPC architecture

— Reset controller

— IEEE 1149.1 test access port (JTAG)

Interrupts

•

— Seven external interrupt request (IRQ) lines

MOTOROLA

MPC862/857T/857DSLHardwareSpeciﬁcations

For More Information On This Product,

Go to: www.freescale.com

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