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MPC750ARX333RH PDF预览

MPC750ARX333RH

更新时间: 2024-01-02 22:45:29
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 外围集成电路
页数 文件大小 规格书
2页 507K
描述
32-BIT, 333MHz, RISC PROCESSOR, CBGA255, CERAMIC, BGA-255

MPC750ARX333RH 技术参数

生命周期:Obsolete零件包装代码:BGA
包装说明:BGA,针数:255
Reach Compliance Code:unknown风险等级:5.72
地址总线宽度:32位大小:32
边界扫描:NO外部数据总线宽度:64
格式:FLOATING POINT集成缓存:YES
JESD-30 代码:S-CBGA-B255低功率模式:YES
端子数量:255最高工作温度:105 °C
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:BGA
封装形状:SQUARE封装形式:GRID ARRAY
认证状态:Not Qualified速度:333 MHz
标称供电电压:1.9 V表面贴装:YES
技术:CMOS端子形式:BALL
端子位置:BOTTOMuPs/uCs/外围集成电路类型:MICROPROCESSOR, RISC
Base Number Matches:1

MPC750ARX333RH 数据手册

 浏览型号MPC750ARX333RH的Datasheet PDF文件第2页 
MPC750FACT/D  
REV. 6  
F a c t S h e e t  
MO T O R O L A PO W E R PC 750A N D  
PO W E R PC 740MI C R O P R O C E S S O R S  
The PowerPC 750 and PowerPC 740 microprocessors are low-power 32-bit implementations of the  
PowerPC Reduced Instruction Set Computer (RISC) architecture. The PowerPC 750 and the PowerPC 740  
microprocessors differ only in that the PowerPC 750 features a dedicated L2 cache interface with on-chip L2  
tags. Both are software-compatible and bus-compatible with the PowerPC 603e™ and MPC7400 micro-  
processors, and the PowerPC 740 is pin-compatible as well. PowerPC 750/740 microprocessors are fully  
JTAG-compliant.  
Motorola PowerPC 750  
Microprocessor  
Superscalar Microprocessor  
The PowerPC 750/740 microprocessors are superscalar, capable  
of issuing three instructions per clock cycle into six independent  
execution units:  
Two integer units  
Load/store unit  
Floating-point unit  
System register unit  
Branch processing unit  
The ability to execute multiple instructions in parallel, to  
pipeline instructions, and the use of simple instructions with  
rapid execution times yields maximum efficiency and throughput  
for PowerPC 750/740 systems.  
Power Management  
The PowerPC 750/740 microprocessors feature a low-  
power 2.6-volt or 1.9-volt design with three power-  
saving modes—doze, nap and sleep. These  
PowerPC 750/740 Microprocessor  
Block Diagram  
user-programmable modes progressively reduce the  
power drawn by the processor.  
System Register  
Unit  
Branch Processing Instruction  
Unit  
Unit  
These low-power microprocessors offer dynamic  
power management to selectively activate functional  
units as they are needed by the executing instructions.  
Both microprocessors also provide a thermal assist unit  
and instruction cache throttling for software-  
controllable thermal management.  
Integer Integer  
Floating Point  
Unit  
Load/Store  
Unit  
Unit  
Unit  
MMU  
Data Cache  
MMU  
Inst. Cache  
Cache and MMU Support  
The PowerPC 750/740 microprocessors have separate  
32-Kbyte, physically-addressed instruction and data  
caches. Both caches are eight-way set-associative.  
Bus Interface Unit  
System Bus  
L2 Control / Tags  
64b  
Data  
32b  
Address  
64b  
Data  
17b  
Address  
The additional dedicated L2 cache interface with on-  
chip L2 tags (shown at right) is provided only by the  
L2 Cache  
MPC750 Only  

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