Datasheet > MPC5602PEF0MLL6R

MPC5602PEF0MLL6R

更新时间： 2022-04-02 12:41:39

品牌	Logo	应用领域
飞思卡尔 - FREESCALE		微控制器 PC
页数	文件大小	规格书
95页	1700K
描述
MPC5602P Microcontroller Data Sheet

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MPC5602PEF0MLL6R 数据手册

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Table 2. MPC5602P series block summary (continued)

Function

Block

Pulse width modulator (FlexPWM) Contains four PWM submodules, each of which capable of controlling a single

half-bridge power stage and two fault input channels

Reset generation module

(MC_RGM)

Centralizes reset sources and manages the device reset sequence of the device

Static random-access memory

(SRAM)

Provides storage for program code, constants, and variables

System integration unit lite (SIUL) Provides control over all the electrical pad controls and up 32 ports with 16 bits

of bidirectional, general-purpose input and output signals and supports up to 32

external interrupts with trigger event configuration

System status and configuration Provides system configuration and status data (such as memory size and status,

module (SSCM)

device mode and security status), device identification data, debug status port

enable and selection, and bus and peripheral abort enable/disable

System timer module (STM)

Provides a set of output compare events to support AUTOSAR¹and operating

system tasks

System watchdog timer (SWT)

Wakeup unit (WKPU)

Provides protection from runaway code

Supports up to 18 external sources that can generate interrupts or wakeup

events, of which 1 can cause non-maskable interrupt requests or wakeup events

AUTOSAR: AUTomotive Open System ARchitecture (see http://www.autosar.org)

Feature details

1.5

1.5.1

High performance e200z0 core processor

The e200z0 Power Architecture core provides the following features:

•

High performance e200z0 core processor for managing peripherals and interrupts

Single issue 4-stage pipeline in-order execution 32-bit Power Architecture CPU

Harvard architecture

Variable length encoding (VLE), allowing mixed 16- and 32-bit instructions

— Results in smaller code size footprint

— Minimizes impact on performance

•

Branch processing acceleration using lookahead instruction buffer

Load/store unit

— 1-cycle load latency

— Misaligned access support

— No load-to-use pipeline bubbles

•

Thirty-two 32-bit general purpose registers (GPRs)

Separate instruction bus and load/store bus Harvard architecture

Hardware vectored interrupt support

Reservation instructions for implementing read-modify-write constructs

Long cycle time instructions, except for guarded loads, do not increase interrupt latency

Extensive system development support through Nexus debug port

Non-maskable interrupt support

MPC5602P Microcontroller Data Sheet, Rev. 4.1

Freescale Semiconductor

1...4 5 678 9 10...95

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