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MM74HCT109N/B+ PDF预览

MM74HCT109N/B+

更新时间： 2024-01-03 17:48:54
品牌 Logo 应用领域
美国国家半导体 - NSC 触发器
页数 文件大小 规格书
4页 117K
描述
IC,FLIP-FLOP,DUAL,J/K TYPE,HCT-CMOS,DIP,16PIN,PLASTIC

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中文翻译

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MM74HCT109N/B+ 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：DIP, DIP16,.3Reach Compliance Code：unknown
风险等级：5.92JESD-30 代码：R-PDIP-T16
JESD-609代码：e0逻辑集成电路类型：J-K FLIP-FLOP
功能数量：2端子数量：16
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP16,.3封装形状：RECTANGULAR
封装形式：IN-LINE电源：5 V
认证状态：Not Qualified子类别：FF/Latches
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
触发器类型：POSITIVE EDGEBase Number Matches：1

MM74HCT109N/B+ 数据手册

 浏览型号MM74HCT109N/B+的Datasheet PDF文件第2页浏览型号MM74HCT109N/B+的Datasheet PDF文件第3页浏览型号MM74HCT109N/B+的Datasheet PDF文件第4页 
January 1988  
MM54HCT109/MM74HCT109  
Dual J-K Flip-Flops with Preset and Clear  
General Description  
These high speed J-K FLIP-FLOPS utilize advanced silicon-  
gate CMOS technology. They possess the low power con-  
sumption and high noise immunity of standard CMOS inte-  
grated circuits, along with the ability to drive 10 LS-TTL  
loads.  
MM54HCT/MM74HCT devices are intended to interface be-  
tween TTL and NMOS components and standard CMOS  
devices. These parts are also plug-in replacements for LS-  
TTL devices and can be used to reduce power consumption  
in existing designs.  
Each flip flop has independent J, K, PRESET, CLEAR, and  
CLOCK inputs and Q and Q outputs. These devices are  
edge sensitive to the clock input and change state on the  
positive going transition of the clock pulse. Clear and preset  
are independent of the clock and accomplished by a low  
logic level on the corresponding input.  
Features  
Y
Typical propagation delay: 20 ns  
Y
Low input current: 1 mA maximum  
Y
Low quiescent current: 40 mA maximum (74HCT Series)  
Y
Output drive capability: 10 LS-TTL loads  
The 54HCT/74HCT logic family is functionally as well as  
pin-out compatible with the standard 54LS/74LS logic fami-  
ly. All inputs are protected from damage due to static dis-  
charge by internal diode clamps to V  
and ground.  
CC  
Connection and Logic Diagrams  
Function Table  
Dual-In-Line Package  
Inputs  
CLK  
Outputs  
PR  
CLR  
J
K
Q
Q
L
H
L
H
L
X
X
X
X
X
L
X
X
X
L
H
L
L
H
L
X
H*  
L
H*  
H
H
H
H
H
H
H
H
H
H
H
u
u
u
u
L
H
L
L
TOGGLE  
H
H
X
Q0  
H
Q0  
L
H
X
Q0  
Q0  
Order Number MM54HCT109 or MM74HCT109  
TL/F/5361–1  
TL/F/5361–2  
C
1995 National Semiconductor Corporation  
TL/F/5361  
RRD-B30M105/Printed in U. S. A.  
1234

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