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MM74HC147

更新时间： 2024-01-27 19:42:27
品牌 Logo 应用领域
美国国家半导体 - NSC 编码器
页数 文件大小 规格书
4页 111K
描述
10-to-4 Line Priority Encoder

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中文翻译

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MM74HC147 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：DIP, DIP16,.3Reach Compliance Code：unknown
风险等级：5.92JESD-30 代码：R-PDIP-T16
JESD-609代码：e0逻辑集成电路类型：ENCODER
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装等效代码：DIP16,.3
封装形状：RECTANGULAR封装形式：IN-LINE
电源：2/6 V认证状态：Not Qualified
子类别：Arithmetic Circuits表面贴装：NO
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
Base Number Matches：1

MM74HC147 数据手册

 浏览型号MM74HC147的Datasheet PDF文件第2页浏览型号MM74HC147的Datasheet PDF文件第3页浏览型号MM74HC147的Datasheet PDF文件第4页 
November 1995  
MM54HC147/MM74HC147  
10-to-4 Line Priority Encoder  
General Description  
This high speed 10-to-4 Line Priority Encoder utilizes ad-  
vanced silicon-gate CMOS technology. It possesses the  
high noise immunity and low power consumption of stan-  
dard CMOS integrated circuits. This device is fully buffered,  
giving it a fanout of 10 LS-TTL loads.  
The 54HC/74HC logic family is functionally as well as pin-  
out compatible with the standard 54LS/74LS logic family.  
All inputs are protected from damage due to static dis-  
charge by internal diode clamps to V  
and ground.  
CC  
Features  
Y
The MM54HC147/MM74HC147 features priority encoding  
of the inputs to ensure that only the highest order data line  
is encoded. Nine input lines are encoded to a four line BCD  
output. The implied decimal zero condition requires no input  
condition as zero is encoded when all nine data lines are at  
a high logic level. All data inputs and outputs are active at  
the low logic level.  
Low quiescent power consumption: 40 mW maximum at  
25 C  
§
Y
Y
Y
High speed: 31 ns propagation delay (typical)  
Low input current: 1 mA maximum  
Wide supply range: 2V to 6V  
Connection and Logic Diagrams  
Dual-In-Line Package  
TL/F/5007–1  
Top View  
Order Number MM54HC147 or MM74HC147  
Truth Table  
Inputs  
Outputs  
1
2
3
4
5
6
7
8
9
D
C
B
A
H
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
L
H
X
X
X
X
X
L
H
X
X
X
X
L
H
X
X
X
L
H
X
X
L
H
X
L
H
L
H
L
H
H
H
L
H
H
H
L
H
L
H
H
H
H
H
H
H
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
L
H
H
H
H
H
L
H
H
L
TL/F/5007–2  
H
H
H
H
L
H
L
H
H
H
H
H
H
H
H
L
H
L
H
H
e
e
e
H
High Logic Level, L  
Low Logic Level, X  
Irrelevant  
C
1995 National Semiconductor Corporation  
TL/F/5007  
RRD-B30M115/Printed in U. S. A.  
1234

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