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MM74C89

更新时间： 2024-02-28 08:32:19
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 存储
页数 文件大小 规格书
6页 63K
描述
64-Bit 3-STATE Random Access Read/Write Memory

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中文翻译

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MM74C89 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：DIP, DIP16,.3Reach Compliance Code：unknown
风险等级：5.92最长访问时间：650 ns
JESD-30 代码：R-PDIP-T16JESD-609代码：e0
内存集成电路类型：STANDARD SRAM内存宽度：4
端子数量：16字数：16 words
字数代码：16工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：16X4输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP16,.3封装形状：RECTANGULAR
封装形式：IN-LINE并行/串行：PARALLEL
电源：5/15 V认证状态：Not Qualified
子类别：SRAMs表面贴装：NO
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL

MM74C89 数据手册

 浏览型号MM74C89的Datasheet PDF文件第2页浏览型号MM74C89的Datasheet PDF文件第3页浏览型号MM74C89的Datasheet PDF文件第4页浏览型号MM74C89的Datasheet PDF文件第5页浏览型号MM74C89的Datasheet PDF文件第6页 
October 1987  
Revised January 1999  
MM74C89  
64-Bit 3-STATE Random Access Read/Write Memory  
Read Operation: The complement of the information  
which was written into the memory is non-destructively  
General Description  
The MM74C89 is a 16-word by 4-bit random access read/  
read out at the four outputs. This is accomplished by  
write memory. Inputs to the memory consist of four address  
selecting the desired address and bringing memory enable  
lines, four data input lines, a write enable line and a mem-  
LOW and write enable HIGH.  
ory enable line. The four binary address inputs are  
When the device is writing or disabled the output assumes  
decoded internally to select each of the 16 possible word  
a 3-STATE (Hi-z) condition.  
locations. An internal address register latches the address  
information on the positive to negative transition of the  
memory enable input. The four 3-STATE data output lines  
working in conjunction with the memory enable input pro-  
vide for easy memory expansion.  
Features  
■ Wide supply voltage range: 3.0V to 15V  
■ Guaranteed noise margin: 1.0V  
Address Operation: Address inputs must be stable tSA  
■ High noise immunity: 0.45 VCC (typ.)  
prior to the positive to negative transition of memory  
enable. It is thus not necessary to hold address information  
stable for more than tHA after the memory is enabled (posi-  
■ Low power TTL compatibility:  
fan out of 2 driving 74L  
■ Low power consumption: 100 nW/package (typ.)  
■ Fast access time: 130 ns (typ.) at VCC = 10V  
tive to negative transition of memory enable).  
Write Operation: Information present at the data inputs is  
written into the memory at the selected address by bringing  
write enable and memory enable LOW.  
■ 3-STATE output  
Note: The timing is different than the DM7489 in that a positive to negative  
transition of the memory enable must occur for the memory to be selected.  
Ordering Code:  
Order Number  
Package Number Package Description  
MM74C89N  
N16E  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
Connection Diagram  
Truth Table  
ME WE  
Operation  
Write  
Read  
Condition of Outputs  
3-STATE  
Complement of Selected Word  
Pin Assignments for DIP  
L
L
L
H
L
H
H
Inhibit, Storage 3-STATE  
Inhibit, Storage 3-STATE  
H
Top View  
© 1999 Fairchild Semiconductor Corporation  
DS005888.prf  
www.fairchildsemi.com  
123456

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与MM74C89相关器件

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MM74C89J NSC

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 		64-Bit TRI-STATE Random Access Read/Write Memory
MM74C89J ROCHESTER

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 		Random Access Read / Write Memory Wide supply voltage range 3.0V ro 15V
MM74C89J/A+ NSC

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 		IC,SRAM,16X4,CMOS,DIP,16PIN,CERAMIC
MM74C89N ROCHESTER

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 		Random Access Read / Write Memory Wide supply voltage range 3.0V ro 15V
MM74C89N FAIRCHILD

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 		64-Bit 3-STATE Random Access Read/Write Memory
MM74C89N NSC

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 		64-Bit TRI-STATE Random Access Read/Write Memory
MM74C90 FAIRCHILD

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 		4-Bit Decade Counter 4-Bit Binary Counter
MM74C90_02 FAIRCHILD

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 		4-Bit Decade Counter
MM74C901 NSC

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 		Hex Inverting TTL, Non-Inverting TTL, Inverting CMOS, Non-Inverting CMOS Buffer
MM74C901 FAIRCHILD

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 		Hex Inverting TTL Buffer . Hex Non-Inverting TTL Buffer

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