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MLX71122RLQ PDF预览

MLX71122RLQ

更新时间： 2024-02-15 08:04:44
品牌 Logo 应用领域
迈来芯 - MELEXIS 电信电信集成电路
页数 文件大小 规格书
59页 2653K
描述
300 to 930MHz FSK/FM/ASK Receiver

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MLX71122RLQ 技术参数

是否Rohs认证： 符合生命周期：Obsolete
包装说明：HVQCCN,Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.62
JESD-30 代码：S-XQCC-N32JESD-609代码：e3
长度：5 mm功能数量：1
端子数量：32最高工作温度：110 °C
最低工作温度：-40 °C封装主体材料：UNSPECIFIED
封装代码：HVQCCN封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度（摄氏度）：NOT SPECIFIED
座面最大高度：1 mm标称供电电压：5 V
表面贴装：YES技术：CMOS
电信集成电路类型：TELECOM CIRCUIT温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：5 mm
Base Number Matches：1

MLX71122RLQ 数据手册

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MLX71122  
300 to 930MHz FSK/FM/ASK Receiver  
Datasheet  
1. Theory of Operation  
1.1. General  
The MLX71122 receiver architecture is based on a double-conversion super-heterodyne approach. The two  
LO signals are derived from an on-chip integer-N PLL frequency synthesizer. The PLL reference frequency is  
derived from a crystal (XTAL). The PLL synthesizer consists of an integrated voltage-controlled oscillator  
with external inductor, a programmable feedback divider chain, a programmable reference divider, a  
phase-frequency detector with a charge pump and an external loop filter.  
In the receiver’s down-conversion chain, two mixers MIX1 and MIX2 are driven by the internal local  
oscillator signals LO1 and LO2, respectively. The second mixer MIX2 is an image-reject mixer. As the first  
intermediate frequency (IF1) is very high (typically above 100 MHz), a reasonably high degree of image  
rejection is provided even without using an RF front-end filter. At applications asking for very high image  
rejections, cost-efficient RF front-end filtering can be realized by using a SAW filter in front of the LNA.  
The receiver signal chain is set up by a low noise amplifier (LNA), two down-conversion mixers (MIX1 and  
MIX2), an on-chip IF filter (IFF) as well as an IF amplifier (IFA). By choosing the required modulation via an  
FSK/ASK switch (at pin MODSEL), either the on-chip FSK demodulator (FSK DEMOD) or the RSSI-based ASK  
detector is selected. A second order data filter (OA1) and a data slicer (OA2) follow the demodulator. The  
data slicer threshold can be generated from the mean-value of the data stream or by means of the positive  
and negative peak detectors (PKDET+/-).  
In general the MLX71122 can be set to shut-down mode, where all receiver functions are completely  
turned off, and to several other operating modes. There are two global operating modes that are  
selectable via the logic level at pin SPISEL:  
8-channel pre-configured mode (ABC mode)  
fully programmable mode (SPI mode).  
In ABC mode the number of frequency channels is limited to eight but no microcontroller programming is  
required. In this case the three lines of the serial programming interface (SPI) are used to select one of the  
eight predefined frequency channels via simple 3-bit parallel programming. Pins ENRX and MODSEL are  
used to enable/disable the receiver and to select FSK or ASK demodulation, respectively.  
SPI mode is recommended for full programming flexibility. In this case the three lines of the SPI are  
configured as a standard 3-wire bus (SDEN, SDTA and SCLK). This allows changing many parameters of the  
receiver, for example more operating modes, channels, frequency resolutions, gains, demodulation types,  
data slicer settings and more. The pin MODSEL has no effect in this mode.  
REVISION 014 – AUGUST, 2016  
Page 6 of 59  
390 10 71122 01  
1...3456789...59

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