ML2302

更新时间： 2024-01-23 08:15:05

品牌	Logo	应用领域
冲电气 - OKI		音频合成器集成电路消费电路商用集成电路先进先出芯片 PC
页数	文件大小	规格书
24页	199K
描述
Recording and Playback LSI with Built-in 2-Bit ADPCM2 Supported FIFO

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技术参数
数据手册

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ML2302 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	TFQFP,	针数：	64
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.2	商用集成电路类型：	SPEECH SYNTHESIZER WITH RCDG
JESD-30 代码：	S-PQFP-G64	长度：	10 mm
功能数量：	1	端子数量：	64
片上内存类型：	FIFO	最高工作温度：	70 °C
最低工作温度：	-10 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	TFQFP	封装形状：	SQUARE
封装形式：	FLATPACK, THIN PROFILE, FINE PITCH	认证状态：	Not Qualified
座面最大高度：	1.2 mm	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	2.7 V	表面贴装：	YES
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
宽度：	10 mm	Base Number Matches：	1

ML2302 数据手册

FEDL2302DIGEST-05

OKI Semiconductor

ML2302

PIN DESCRIPTIONS

(TQFP)

Symbol

D7 to 0

Type

I/O

Description

(WCSP)

H2, G2,

F2, G1,

F3, F1,

E2, E1

Bidirectional data bus.

Command and data inputs from an external microcontroller and

memory, and status and data outputs to an external

microcontroller and memory.

1 to 8

Write pulse input pin. This pin pulses “L” when command or

voice data is input to D7 to D0 pins.

Read pulse input pin. This pin pulses “L” when status or voice

data is output to D7 to D0.

Accepts write pulse and read pulse when this pin is “L”.

Voice data is input or output to and from D7 to D0 when this pin

is “H”.

D/C

This pin outputs a “L” level during RECORDING, PLAYBACK,

or PAUSE.

BUSY

CBUSY

Accepts a command during this pin is “H”.

“H” indicates that there is no data in FIFO memory.

During playback, voice synthesis starts when EMP changes to

“L”. Active “H” can be changed to active “L”.

“H” level indicates that there is more than half of the FIFO

memory.

EMP

MID

“H” level indicates that FIFO memory is full of data. During

playback, this pin is “H” and data cannot be written in FIFO

memory. During recording, data is not written after FIFO

memory is full of data.

FUL

Active “H” can be changed to active “L”.

This pin should be set at a “L” level normally and be set at a “H”

level when DMA is used.

When DMA transfer is selected, “H” level DREQL outputs a

signal to request a DMA transfer. Active “H” can be changed to

active “L”.

DREQL

Input to DACKL a signal when DMA transfer is permitted by the

DMA controller. when DACKL is “L”, IOW and IOR signals are

accepted.

DACKL

Active “L” can be changed to active “H” by command input.

If DMA transfer is not used, set this pin to “H” level.

Write pulse Input pin to write external memory data to ML2302

during DMA transfer. If DMA transfer is not used, set this pin to

“H” level.

IOW

IOR

Read pulse input pin to read data of ML2302 during DMA

transfer.

If DMA transfer is not used, set this pin to “H” level.

16-bit serial data input pin when external A/D converter is used.

If external A/D converter is not used, set this pin to “L” level.

16-bit serial data input pin when external D/A converter is used.

ADSD

DASD

5/24

1 2 3 456 7 8...24

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