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ML2254

更新时间： 2024-01-06 09:56:51
品牌 Logo 应用领域
冲电气 - OKI 语音合成PC
页数 文件大小 规格书
31页 197K
描述
2-Channel Mixing Oki ADPCM Algorithm-Based Speech Synthesis LSI

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ML2254 技术参数

生命周期：Transferred零件包装代码：LGA
包装说明：VFBGA,针数：33
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.17Is Samacsys：N
其他特性：ALSO OPERATES AT 5V SUPPLY商用集成电路类型：SPEECH SYNTHESIZER
JESD-30 代码：R-PBGA-B33长度：5.78 mm
功能数量：1端子数量：33
片上内存类型：MASK ROM最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：VFBGA封装形状：RECTANGULAR
封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH认证状态：Not Qualified
最长读取时间：261.1 s座面最大高度：0.52 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.7 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：BALL
端子节距：0.8 mm端子位置：BOTTOM
宽度：5.03 mmBase Number Matches：1

ML2254 数据手册

 浏览型号ML2254的Datasheet PDF文件第7页浏览型号ML2254的Datasheet PDF文件第8页浏览型号ML2254的Datasheet PDF文件第9页浏览型号ML2254的Datasheet PDF文件第11页浏览型号ML2254的Datasheet PDF文件第12页浏览型号ML2254的Datasheet PDF文件第13页 
FEDL2250DIGEST-01  
OKI Semiconductor  
ML2252/54-XXX, ML22Q54  
PIN DESCRIPTIONS-2  
ML22Q54 Pins  
44-pin plastic QFP  
Pin  
43  
Symbol  
Type  
O
Description  
When using the built-in ROM for voice output, this pin outputs “L” level  
while channel 2 side processes a command and while plays back voice.  
Works as ERR pin when using EXT command for the voice output. If an  
abnormality occurred in the transfer of data, the ERR pin outputs “L”  
level and the voice output may become noisy.  
BUSY2/ERR  
“H” level at power on.  
Outputs “L” level while the channel 1 side processes a command and  
while plays back voice.  
“H” level at power on.  
3
4
BUSY1  
O
O
The input command of channel 2 is valid at “H” level when using the  
built-in ROM for voice output.  
NCR2/DL  
DL pin when using EXT command for the voice output. It outputs the  
voice data capture signal. The data is captured on the rising edge of DL.  
“H” level at power on.  
The command input of channel 1 side is valid at “H” level when using  
the built-in ROM for voice output.  
5
NCR1/NDR  
O
NDR pin when using EXT command for the voice output. The voice data  
input is effective at “H” level.  
“H” level at power on.  
When “L” level is input to this pin, the device is reset, the oscillation  
stops, and AOUT and DAQ outputs go into GND level.  
9
RESET  
I
I
Test pin for the device.  
Input “L” level to this pin. This pin has a pull-down resistor built in.  
Wired to a crystal or ceramic oscillator.  
10  
TEST  
A feedback resistor of around 1 MΩ is built in between this XT pin and  
XT pin (pin 15).  
14  
15  
XT  
I
When using an external clock, input the clock from this pin.  
Wired to a ceramic or crystal oscillator.  
XT  
O
When using an external clock, keep this pin open.  
CPU interface data bus pins in the parallel input interface.  
Channel status output pins when RD is at “L” level.  
The pins output the flash memory data when reading the built-in flash  
memory data.  
In the serial input interface, keep these pins at “L” level.  
CPU interface data bus pin in the parallel input interface.  
The pin outputs flash memory data when reading the built-in flash  
memory data.  
D3  
D2  
D1  
D0  
16, 18, 19, 20  
I/O  
I/O  
21  
D4  
When RD is at “L” level other than when reading the flash memory data,  
this pin usually outputs “L” level.  
In the serial input interface, keep this pin at “L” level.  
CPU interface data bus pin in the parallel input interface.  
The pin outputs flash memory data when reading the built-in flash  
memory data.  
When RD is at “L” level other than when reading the flash memory data,  
this pin usually outputs “L” level.  
Channel status output pin in the serial input interface.  
23  
D5/DO  
I/O  
When CS and RD are at “L” level, this D5/DO pin serially outputs the  
status of each channel in synchronization with SCK clock. When  
reading data of the built-in flash memory, the pin will output serially the  
flash memory data.  
10/31  
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