Datasheet > ML145151_08

ML145151_08

更新时间： 2022-02-26 09:41:46

品牌	Logo	应用领域
LANSDALE		/
页数	文件大小	规格书
35页	536K
描述
PLL Frequency Synthesizer Family

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ML145151_08 数据手册

LANSDALE Semiconductor, Inc.

ML145151

ML145151 BLOCK DIAGRAM

RA2

RA1

14 x 8 ROM REFERENCE DECODER

OSC

out

RA0

LOCK

DETECT

OSC

14–BIT

R COUNTER

PHASE

DETECTOR

out

14–BIT

N COUNTER

PHASE

DETECTOR

TRANSMIT OFFSET ADDER

T/R

N13

N11

N7 N6

NOTE: N0 – N13 inputs and inputs RA0, RA1, and RA2 have pull–up resistors that are not shown.

PIN DESCRIPTIONS

nificant and N13 is the most significant. Pull–up resistors en-

sure that inputs left open remain at a logic 1 and require only

an SPST switch to alter data to the zero state.

INPUT PINS

Frequency Input (Pin 1)

T/R

Transmit/Receive Offset Adder Input (Pin 21)

Input to the ÷N portion of the synthesizer. f is typically

This input controls the offset added to the data provided at

the N inputs. This is normally used for offsetting the V

quency by an amount equal to the IF frequency of the trans-

ceiver. This offset is fixed at 856 when T/R is low and gives no

offset when T/R is high. A pull–up resistor ensures that no

connection will appear as a logic 1 causing no offset addition.

derived from loop V

and is AC coupled into the device. For

fre-

larger amplitude signals (standard CMOS logic levels) DC

coupling may be used.

RA0 – RA2

Reference Address Inputs (Pins 5, 6, 7)

These three inputs establish a code defining one of eight

possible divide values for the total reference divider, as defined

by the table below.

Pull–up resistors ensure that inputs left open remain at a

logic 1 and require only a SPST switch to alter data to the zero

state.

OSC , OSC

out

Reference Oscillator Input/Output (Pins 27, 26)

These pins form an on–chip reference oscillator when con-

nected to terminals of an external parallel resonant crystal.

Frequency setting capacitors of appropriate value must be con-

nected from OSC to ground and OSC

may also serve as the input for an externally generated refer-

ence signal. This signal is typically AC coupled to OSC , but

for larger amplitude signals (standard CMOS logic levels) DC

coupling may also be used. In the external reference mode, no

to ground. OSC

out

Total

Divide

Value

Reference Address Code

RA2

RA1

RA0

128

256

512

1024

2048

2410

8192

connection is required to OSC

OUTPUT PINS

PDout

out

Phase Detector A Output (Pin 4)

Three–state output of phase detector for use as loop–error

signal. Double–ended outputs are also available for this pur-

pose (see ΦV and ΦR).

N0 – N11

Frequency f > f or f Leading: Negative Pulses

Frequency f < f or f Lagging: Positive Pulses

Frequency f = f and Phase Coincidence: High–Imped-

N Counter Programming Inputs (Pins 11 – 20, 22 – 25)

These inputs provide the data that is preset into the ÷ N

counter when it reaches the count of zero. N0 is the least sig-

ance State

Page 3 of 35

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Issue A

1 234 5 6 7...35

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与ML145151_08相关器件

型号	品牌	描述	获取价格	数据表
ML145151-6P	LANSDALE	Parallel-Input PLL Frequency Synthesizer Interfaces with Single-Modulus Prescalers	获取价格
ML145151YP	LANSDALE	Parallel-Input PLL Frequency Synthesizer Interfaces with Single-Modulus Prescalers	获取价格
ML145152	LANSDALE	Parallel-Input PLL Frequency Synthesizer Interfaces with Single-Modulus Prescalers	获取价格
ML145152-6P	LANSDALE	PLL Frequency Synthesizer Family	获取价格
ML145152YP	LANSDALE	PLL Frequency Synthesizer Family	获取价格
ML145155	LANSDALE	Parallel-Input PLL Frequency Synthesizer Interfaces with Single-Modulus Prescalers	获取价格

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