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MK30DX128ZVLQ10 PDF预览

MK30DX128ZVLQ10

更新时间: 2024-01-26 20:12:11
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飞思卡尔 - FREESCALE /
页数 文件大小 规格书
72页 1924K
描述
K30 Sub-Family Data Sheet

MK30DX128ZVLQ10 技术参数

是否Rohs认证:符合生命周期:Transferred
零件包装代码:QFP包装说明:20 X 20 MM, LQFP-144
针数:144Reach Compliance Code:compliant
ECCN代码:3A001.A.3HTS代码:8542.31.00.01
风险等级:5.71Is Samacsys:N
具有ADC:YES地址总线宽度:
位大小:32CPU系列:CORTEX-M4
最大时钟频率:50 MHzDAC 通道:YES
DMA 通道:YES外部数据总线宽度:
JESD-30 代码:S-PQFP-G144长度:20 mm
I/O 线路数量:100端子数量:144
最高工作温度:105 °C最低工作温度:-40 °C
PWM 通道:YES封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装等效代码:QFP144,.87SQ,20
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
电源:1.8/3.3 V认证状态:Not Qualified
RAM(字节):32768ROM(单词):131072
ROM可编程性:FLASH座面最大高度:1.6 mm
速度:100 MHz子类别:Microcontrollers
最大供电电压:3.6 V最小供电电压:1.71 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD宽度:20 mm
uPs/uCs/外围集成电路类型:MICROCONTROLLER, RISCBase Number Matches:1

MK30DX128ZVLQ10 数据手册

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Document Number: K30P144M100SF2  
Rev. 6, 9/2011  
Freescale Semiconductor  
Data Sheet: Technical Data  
K30P144M100SF2  
K30 Sub-Family Data Sheet  
Supports the following:  
MK30DX128ZVLQ10,  
MK30DX128ZVMD10,  
MK30DX256ZVLQ10,  
MK30DX256ZVMD10,  
MK30DN512ZVLQ10,  
MK30DN512ZVMD10  
Features  
Security and integrity modules  
– Hardware CRC module to support fast cyclic  
redundancy checks  
Operating Characteristics  
– Voltage range: 1.71 to 3.6 V  
– Flash write voltage range: 1.71 to 3.6 V  
– Temperature range (ambient): -40 to 105°C  
– 128-bit unique identification (ID) number per chip  
Human-machine interface  
Performance  
– Segment LCD controller supporting up to 40  
frontplanes and 8 backplanes, or 44 frontplanes and  
4 backplanes  
– Low-power hardware touch sensor interface (TSI)  
– General-purpose input/output  
– Up to 100 MHz ARM Cortex-M4 core with DSP  
instructions delivering 1.25 Dhrystone MIPS per  
MHz  
Memories and memory interfaces  
– Up to 512 KB program flash memory on non-  
FlexMemory devices  
Analog modules  
– Two 16-bit SAR ADCs  
– Up to 128 KB RAM  
– Serial programming interface (EzPort)  
– FlexBus external bus interface  
– Programmable gain amplifier (PGA) (up to x64)  
integrated into each ADC  
– Two 12-bit DACs  
– Three analog comparators (CMP) containing a 6-bit  
DAC and programmable reference input  
– Voltage reference  
Clocks  
– 3 to 32 MHz crystal oscillator  
– 32 kHz crystal oscillator  
– Multi-purpose clock generator  
Timers  
– Programmable delay block  
– Eight-channel motor control/general purpose/PWM  
timer  
– Two 2-channel quadrature decoder/general purpose  
timers  
– Periodic interrupt timers  
– 16-bit low-power timer  
– Carrier modulator transmitter  
– Real-time clock  
System peripherals  
– 10 low-power modes to provide power optimization  
based on application requirements  
– Memory protection unit with multi-master  
protection  
– 16-channel DMA controller, supporting up to 64  
request sources  
– External watchdog monitor  
– Software watchdog  
– Low-leakage wakeup unit  
Freescale reserves the right to change the detail specifications as may be  
required to permit improvements in the design of its products.  
© 2010–2011 Freescale Semiconductor, Inc.  

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