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MK1726-02AGTRLF PDF预览

MK1726-02AGTRLF

更新时间： 2024-01-24 12:51:17
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
8页 162K
描述
Clock Generator, 64MHz, CMOS, PDSO8, TSSOP-8

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MK1726-02AGTRLF 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SOIC包装说明：TSSOP-8
针数：8Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.77JESD-30 代码：R-PDSO-G8
JESD-609代码：e3长度：4.4 mm
端子数量：8最高工作温度：85 °C
最低工作温度：最大输出时钟频率：64 MHz
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：NOT SPECIFIED主时钟/晶体标称频率：32 MHz
认证状态：Not Qualified座面最大高度：1.2 mm
最大供电电压：3.63 V最小供电电压：3 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：OTHER
端子面层：MATTE TIN端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：3 mm
uPs/uCs/外围集成电路类型：CLOCK GENERATOR, OTHERBase Number Matches：1

MK1726-02AGTRLF 数据手册

 浏览型号MK1726-02AGTRLF的Datasheet PDF文件第1页浏览型号MK1726-02AGTRLF的Datasheet PDF文件第2页浏览型号MK1726-02AGTRLF的Datasheet PDF文件第4页浏览型号MK1726-02AGTRLF的Datasheet PDF文件第5页浏览型号MK1726-02AGTRLF的Datasheet PDF文件第6页浏览型号MK1726-02AGTRLF的Datasheet PDF文件第7页 
MK1726A  
Low EMI Clock Generator  
Pin Descriptions  
Pin  
Number  
Pin  
Name  
Pin Type  
Pin Description  
Connect to 4-32 MHz crystal or clock.  
1
2
3
X1/ICLK  
GND  
S1  
Input  
Power Connect to ground.  
Input  
Function select 1 input. Selects spread amount and direction per table above.  
(default-internal mid-level).  
4
S0  
Input  
Function select 0 input. Selects spread amount and direction per table above.  
(default-internal mid-level).  
5
6
7
8
SSCLK  
FRSEL  
VDD  
Output Clock output with Spread spectrum  
Input Function select for input frequency range. Default to mid level “M”.  
Power Connect to +3.3 V.  
XO Crystal connection to 4-32 MHz crystal. Leave unconnected for clock  
X2  
PCB Layout Recommendations  
External Components  
For optimum device performance and lowest output  
phase noise, observe the following guidelines:  
The MK1726-01A/-02A/-04A devices require a  
minimum number of external components for proper  
operation.  
1) Mount the 0.01µF decoupling capacitor on the  
component side of the board as close to the VDD pin  
as possible. No vias should be used between the  
decoupling capacitor and VDD pin. The PCB trace to  
the VDD pin and the PCB trace to the ground via  
should be kept as short as possible.  
Decoupling Capacitor  
A decoupling capacitor of 0.01µF must be connected  
between VDD and GND on pins 7 and 2. Connect the  
capacitor as close to these pins as possible. For  
optimum device performance, mount the decoupling  
capacitor on the component side of the PCB. Avoid the  
use of vias in the decoupling circuit.  
2) To minimize EMI, place the 33Ω series-termination  
resistor (if needed) close to the clock output.  
3) An optimum layout is one with all components on the  
same side of the board, thus minimizing vias through  
other signal layers. Other signal traces should be  
routed away from the MK1726A devices. This includes  
signal traces located underneath the device, or on  
layers adjacent to the ground plane layer used by the  
device.  
Series Termination Resistor  
Use series termination when the PCB trace between  
the clock output and the load is over 1 inch. To series  
terminate a 50Ω trace (a commonly used trace  
impedance), place a 33Ω resistor in series with the  
clock line. Place the resistor as close to the clock  
output pin as possible. The nominal impedance of the  
clock output is 20Ω.  
Crystal Information  
The crystal used should be a fundamental mode (do  
not use third overtone), parallel resonant crystal. To  
optimize the initial accuracy, connect crystal capacitors  
from pins X1 to ground and X2 to ground. The value of  
these capacitors is given by the following equation:  
Tri-level Select Pin Operation  
The S1 and S0 select pins are tri-level, meaning that  
they have three separate states to make the selections  
shown in the table on page 2. To select the M (mid)  
level, the connection to these pins must be eliminated  
by either floating them originally, or tri-stating the GPIO  
pins which drive the select pins.  
Crystal caps (pF) = (C - 6) x 2  
L
MDS 1726A B  
3
Revision 101703  
Integrated Circuit Systems, Inc. z 525 Race Street, San Jose, CA 95126 z tel (408) 297-1201 z www.icst.com  
12345678

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