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MGA-637P8 PDF预览

MGA-637P8

更新时间: 2024-02-15 10:46:35
品牌 Logo 应用领域
安华高科 - AVAGO 放大器功率放大器
页数 文件大小 规格书
14页 161K
描述
High Linearity Low Noise Amplifi er

MGA-637P8 数据手册

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MGA-637P8  
High Linearity Low Noise Amplifier  
Data Sheet  
Description  
Features  
Avago Technologies’ MGA-637P8 is an economical, easy-  High linearity performance.  
to-use GaAs MMIC Low Noise Amplifier (LNA). This LNA  
has low noise and high linearity achieved through the  
use of Avago Technologies’ proprietary 0.25 m GaAs  
 Low Noise Figure.  
[1]  
 GaAs E-pHEMT Technology  
.
Enhancement-mode pHEMT process. It is housed in the  Low cost small package size.  
3
miniature 2.0 x 2.0 x 0.75 mm 8-pin Dual-Flat-Non-Lead  
 Integrated with active bias and option to access FET  
(DFN) package. The device is designed for optimum use  
from 1.5 GHz up to 2.5 GHz. The compact footprint and  
low profile coupled with low noise, high gain and high  
linearity make this an ideal choice as a low noise amplifier  
for cellular infrastructure applications such as LTE, GSM,  
CDMA, W-CDMA, CDMA2000 & TD-SCDMA. For optimum  
performance at lower frequency from 450 MHz up to  
1.5 GHz, MGA-636P8 is recommended. For optimum  
performance at higher frequency from 2.5 GHz up to  
4 GHz, MGA-638P8 is recommended. All these 3 products,  
MGA-636P8, MGA-637P8 and MGA-638P8 share the same  
package and pinout configuration.  
gate.  
 Integrated power down control pin.  
Specifications  
1.7 GHz; 4.8 V, 75 mA  
 17.3 dB Gain  
 0.52 dB Noise Figure  
 11 dB Input Return Loss  
 22.5 dBm Input IP3  
 21.9 dBm Output Power at 1 dB gain compression  
Pin Configuration and Package Marking  
Applications  
3
2.0 x 2.0 x 0.75 mm 8-lead DFN  
 Cellular infrastructure applications such as LTE, GSM,  
[1]  
[8]  
[7]  
CDMA, W-CDMA, CDMA2000 & TD-SCDMA.  
[8]  
[7]  
[1]  
[2]  
[2]  
[3]  
[4]  
 Other low noise applications.  
37X  
GND  
[6]  
[5]  
[3]  
[4]  
[6]  
[5]  
Note:  
1. Enhancement mode technology employs positive Vgs, thereby  
eliminating the need of negative gate voltage associated with con-  
ventional depletion mode devices.  
TOP VIEW  
BOTTOM VIEW  
Pin 1 – Not Used  
Pin 2 – RFinput  
Pin 3 – Vbias2  
Pin 5 – Vbias1  
Pin 6 – PwrDwn  
Pin 7 – RFoutput  
Pin 8 – Not Used  
Pin 4 – Not Used  
Center paddle – GND  
Attention: Observe precautions for  
handling electrostatic sensitive devices.  
ESD Machine Model = 80 V  
ESD Human Body Model = 350 V  
Refer to Avago Application Note A004R:  
Electrostatic Discharge, Damage and Control.  
Note:  
Package marking provides orientation and identification  
“37= Product Code  
“X” = Month Code  
It is recommended to ground Pin1, 4 and 8 which are Not Used.  

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