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MCZ33937EK PDF预览

MCZ33937EK

更新时间： 2024-01-07 17:13:47
品牌 Logo 应用领域
恩智浦 - NXP 电动机控制光电二极管
页数 文件大小 规格书
48页 655K
描述
AC MOTOR CONTROLLER, 0.8A, PDSO54, 0.65 MM PITCH, ROHS COMPLIANT, SOIC-54

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MCZ33937EK 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SOIC包装说明：0.65 MM PITCH, ROHS COMPLIANT, SOIC-54
针数：54Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8541.29.00.95
风险等级：5.82模拟集成电路 - 其他类型：AC MOTOR CONTROLLER
JESD-30 代码：R-PDSO-G54JESD-609代码：e3
长度：17.9 mm湿度敏感等级：3
功能数量：1端子数量：54
最高工作温度：135 °C最低工作温度：-40 °C
最大输出电流：0.8 A封装主体材料：PLASTIC/EPOXY
封装代码：HSSOP封装等效代码：SSOP54,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, HEAT SINK/SLUG, SHRINK PITCH
峰值回流温度（摄氏度）：NOT SPECIFIED电源：8/40 V
认证状态：Not Qualified座面最大高度：2.45 mm
子类别：Motion Control Electronics最大供电电压 (Vsup)：40 V
最小供电电压 (Vsup)：8 V标称供电电压 (Vsup)：14 V
表面贴装：YES技术：MOS
温度等级：AUTOMOTIVE端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.5 mmBase Number Matches：1

MCZ33937EK 数据手册

 浏览型号MCZ33937EK的Datasheet PDF文件第1页浏览型号MCZ33937EK的Datasheet PDF文件第2页浏览型号MCZ33937EK的Datasheet PDF文件第3页浏览型号MCZ33937EK的Datasheet PDF文件第5页浏览型号MCZ33937EK的Datasheet PDF文件第6页浏览型号MCZ33937EK的Datasheet PDF文件第7页 
PIN CONNECTIONS  
Table 1. 33937A Pin Definitions (continued)  
A functional description of each pin can be found in the Functional Pin Description section beginning on page 20.  
Pin  
Pin Name Pin Function  
Formal Name  
Definition  
Active low input logic signal enables the High Side Driver for Phase A  
Active high input logic signal enables the Low Side Driver for Phase A  
VDD regulator output capacitor connection.  
12  
13  
PA_HS  
PA_LS  
VDD  
Digital Input  
Digital Input  
Analog Output  
Digital Input  
Digital Input  
Digital Output  
Digital Input  
Digital Input  
Digital Input  
Digital Output  
Digital Input  
Digital Input  
Phase A High Side  
Phase A Low Side  
VDD Regulator  
Phase B High Side  
Phase B Low Side  
Interrupt  
14  
Active low input logic signal enables the High Side Driver for Phase B  
Active high input logic signal enables the Low Side Driver for Phase B  
Interrupt pin output  
15  
PB_HS  
PB_LS  
INT  
16  
17  
Chip Select input. It frames SPI commands and enables SPI port  
Input data for SPI port. Clocked on the falling edge of SCLK, MSB first  
Clock for SPI port and typically is 3.0 MHz  
18  
CS  
Chip Select  
19  
SI  
Serial In  
20  
SCLK  
SO  
Serial Clock  
Output data for SPI port. Tri-state until CS becomes low  
Active high input logic signal enables the Low Side Driver for Phase C  
Active low input logic signal enables the High Side Driver for Phase C  
Output of the current-sensing amplifier  
21  
Serial Out  
22  
PC_LS  
PC_HS  
Phase C Low Side  
Phase C High Side  
Amplifier Output  
Amplifier Invert  
Amplifier Non-Invert  
Over-current Out  
23  
24  
AMP_OUT Analog Output  
Inverting input of the current-sensing amplifier  
25  
AMP_N  
AMP_P  
OC_OUT  
OC_TH  
VSS  
Analog Input  
Analog Input  
Digital Output  
Non-inverting input of the current-sensing amplifier  
Totem pole digital output of the Over-current Comparator  
Threshold of the over-current detector  
26  
27  
28  
Analog Input Over-current Threshold  
Ground reference for logic interface and power supplies  
Substrate and ESD reference, connect to VSS  
29  
Ground  
Ground  
Voltage Source Supply  
Ground  
30, 31  
32  
GND  
VLS Regulator connection for additional output capacitor, providing low-  
impedance supply source for Low Side Gate Drive  
VLS_CAP Analog Output VLS Regulator Output  
Capacitor  
Source connection for Phase C Low Side FET  
34  
35  
36  
37  
PC_LS_S  
Power Input  
Phase C Low Side  
Source  
Gate drive output for Phase C Low Side  
PC_LS_G Power Output Phase C Low Side Gate  
Drive  
Source connection for Phase C High Side FET  
Gate Drive for output Phase C High Side FET  
PC_HS_S  
Power Input  
Phase C High Side  
Source  
PC_HS_G Power Output Phase C High Side  
Gate Drive  
Bootstrap capacitor for Phase C  
38  
39  
PC_BOOT Analog Input  
PB_LS_S Power Input  
Phase C Bootstrap  
Source connection for Phase B Low Side FET  
Phase B Low Side  
Source  
Gate Drive for output Phase B Low Side  
Source connection for Phase B High Side FET  
Gate Drive for output Phase B High Side  
40  
41  
42  
PB_LS_G Power Output Phase B Low Side Gate  
Drive  
PB_HS_S  
Power Input  
Phase B High Side  
Source  
PB_HS_G Power Output  
Phase B High Side  
Gate Drive  
Bootstrap capacitor for Phase B  
43  
44  
PB_BOOT  
PA_LS_S  
Analog Input  
Power Input  
Phase B Bootstrap  
Source connection for Phase A Low Side FET  
Phase A Low Side  
Source  
33937A  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
4
1234567...48

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