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MCM72BA32SG60 PDF预览

MCM72BA32SG60

更新时间: 2024-09-29 22:12:39
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 存储内存集成电路静态存储器信息通信管理
页数 文件大小 规格书
14页 240K
描述
256KB and 512KB BurstRAM Secondary Cache Module for Pentium

MCM72BA32SG60 技术参数

生命周期:Obsolete零件包装代码:DIMM
包装说明:DIMM, DIMM136针数:136
Reach Compliance Code:unknownECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.84
Is Samacsys:N最长访问时间:10 ns
其他特性:BYTE WRITE; BURST COUNTER备用内存宽度:72
JESD-30 代码:R-XDMA-N136内存密度:2359296 bit
内存集成电路类型:CACHE SRAM MODULE内存宽度:36
功能数量:1端口数量:1
端子数量:136字数:65536 words
字数代码:64000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:64KX36输出特性:3-STATE
可输出:YES封装主体材料:UNSPECIFIED
封装形状:RECTANGULAR封装形式:MICROELECTRONIC ASSEMBLY
并行/串行:PARALLEL认证状态:Not Qualified
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:BICMOS温度等级:COMMERCIAL
端子形式:NO LEAD端子位置:DUAL
Base Number Matches:1

MCM72BA32SG60 数据手册

 浏览型号MCM72BA32SG60的Datasheet PDF文件第2页浏览型号MCM72BA32SG60的Datasheet PDF文件第3页浏览型号MCM72BA32SG60的Datasheet PDF文件第4页浏览型号MCM72BA32SG60的Datasheet PDF文件第5页浏览型号MCM72BA32SG60的Datasheet PDF文件第6页浏览型号MCM72BA32SG60的Datasheet PDF文件第7页 
Order this document  
by MCM72BA32/D  
SEMICONDUCTOR TECHNICAL DATA  
MCM72BA32  
MCM72BA64  
256KB and 512KB BurstRAM  
Secondary Cache Module for  
Pentium  
136–LEAD DIMM  
CASE 1104–01  
TOP VIEW  
The MCM72BA32SG and MCM72BA64SG are designed to provide a burst-  
able, high performance, 256K/512K L2 cache for the Pentium microprocessor.  
The modules are configured as 32K x 72 and 64K x 72 bits in a 136 pin dual read-  
out single inline memory module (DIMM). The module uses four of Motorola’s  
MCM67B518 or MCM67B618 BiCMOS BurstRAMs.  
1
Bursts canbeinitiatedwitheitheraddressstatusprocessor(ADSP) or address  
status controller (ADSC). Subsequent burst addresses are generated internal to  
the BurstRAM by the burst advance (ADV) input pin.  
Write cycles are internally self timed and are initiated by the rising edge of the  
clock (K) input. Eight write enables are provided for byte write control.  
The cache family is designed to interface with popular Pentium cache control-  
lers with on board TAG.  
PD0 – PD2 are reserved for density and speed identification.  
34  
35  
Pentium–style Burst Counter on Board  
Dual Readout SIMM for Circuit Density  
Single 5 V ± 5% Power Supply  
All Inputs and Outputs are TTL Compatible  
Three State Outputs  
Byte Parity  
Byte Write Capability  
68  
Fast Module Clock Rates: 66 MHz, 60 MHz, 50MHz  
Decoupling Capacitors for each Fast Static RAM  
High Quality Multi–Layer FR4 PWB With Separate Power and Ground Planes  
I/Os are 3.3 V Compatible  
BurstRAM is a trademark of Motorola.  
Pentium is a trademark of Intel Corp.  
REV 2  
5/95  
Motorola, Inc. 1995  

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