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MC9S12XET256VAL PDF预览

MC9S12XET256VAL

更新时间: 2024-01-18 18:36:37
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
15页 3828K
描述
16-bit MCU, S12X core, 256KB Flash, 50MHz, -40/+105degC, QFP 112

MC9S12XET256VAL 数据手册

 浏览型号MC9S12XET256VAL的Datasheet PDF文件第4页浏览型号MC9S12XET256VAL的Datasheet PDF文件第5页浏览型号MC9S12XET256VAL的Datasheet PDF文件第6页浏览型号MC9S12XET256VAL的Datasheet PDF文件第8页浏览型号MC9S12XET256VAL的Datasheet PDF文件第9页浏览型号MC9S12XET256VAL的Datasheet PDF文件第10页 
Features  
• 1-bit fault correction  
• 2-bit fault detection  
• Improved EMC performance  
• Separate supply for internal voltage regulator and I/O allow optimized EMC filtering  
• Enhanced current consumption  
• Extended API up to 5 sec  
3.5 Module Features  
The following sections provide more details of the modules implemented on the MC9S12XE.  
3.5.1 16-Bit CPU12X  
• 16-bit CPU12X  
• Compatible with MC9S12 instruction set with the exception of five fuzzy instructions (MEM, WAV, WAVR, REV,  
REVW) which have been removed.  
• Enhanced indexed addressing  
• Access to large data segments independent of PPAGE  
3.5.2 Enhanced Interrupt Module  
• Eight levels of nested interrupts  
• Flexible assignment of interrupt sources to each interrupt level.  
• External non-maskable high priority interrupt (XIRQ)  
• Internal, non-maskable high priority memory protection unit interrupt  
• Up to 24 pins on ports J, H and P configurable as rising or falling edge sensitive  
3.5.3 XGATE  
• Programmable, high performance I/O coprocessor module with up to 100 MIPS RISC performance  
• Transfers data to or from all peripherals and RAM without CPU intervention or CPU wait states  
• Performs logical, shifts, arithmetic, and bit operations on data  
• Can interrupt the S12X CPU signalling transfer completion  
• Triggers from any hardware module as well as from the CPU possible  
• Two interrupt levels to service high priority tasks  
• Enables Full CAN capability when used in conjunction with MSCAN module  
• Full LIN master or slave capability when used in conjunction with the integrated LIN SCI modules  
3.5.4 Memory Protection Unit (MPU)  
• 8 address regions definable per active program task  
• Address range granularity as low as 8-bytes  
• Protection Attributes  
• No write  
• No execute  
MC9S12XE Family Product Brief, Rev. 9, 4/2015  
Freescale Semiconductor, Inc.  
7
 

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