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MC74LVX139_14 PDF预览

MC74LVX139_14

更新时间: 2024-01-27 17:34:04
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
7页 121K
描述
Dual 2-to-4 Decoder/ Demultiplexer

MC74LVX139_14 数据手册

 浏览型号MC74LVX139_14的Datasheet PDF文件第2页浏览型号MC74LVX139_14的Datasheet PDF文件第3页浏览型号MC74LVX139_14的Datasheet PDF文件第4页浏览型号MC74LVX139_14的Datasheet PDF文件第5页浏览型号MC74LVX139_14的Datasheet PDF文件第6页浏览型号MC74LVX139_14的Datasheet PDF文件第7页 
MC74LVX139  
Dual 2-to-4 Decoder/  
Demultiplexer  
The MC74LVX139 is an advanced high speed CMOS 2−to−4  
decoder/demultiplexer fabricated with silicon gate CMOS technology.  
When the device is enabled (E = low), it can be used for gating or as  
a data input for demultiplexing operations. When the enable input is  
held high, all four outputs are fixed high, independent of other inputs.  
The inputs tolerate voltages up to 7.0 V, allowing the interface of  
5.0 V systems to 3.0 V systems.  
http://onsemi.com  
SOIC−16  
D SUFFIX  
CASE 751B  
TSSOP−16  
DT SUFFIX  
CASE 948F  
Features  
High Speed: t = 6.0 ns (Typ) at V = 3.3 V  
PD  
CC  
Low Power Dissipation: I = 4 mΑ (Max) at T = 25°C  
CC  
A
PIN ASSIGNMENT  
High Noise Immunity: V  
= V = 28% V  
NIL CC  
NIH  
V
CC  
Eb A0b A1b Y0b Y1b Y2b Y3b  
Power Down Protection Provided on Inputs  
Balanced Propagation Delays  
16 15 14 13 12 11 10  
9
Designed for 2 V to 3.6 V Operating Range  
Low Noise: V  
= 0.5 V (Max)  
OLP  
1
2
3
4
5
6
7
8
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300 mA  
Ea A0a A1a Y0a Y1a Y2aY3a GND  
Chip Complexity: 100 FETs or 25 Equivalent Gates  
MARKING DIAGRAMS  
ESD Performance:  
16  
Human Body Model > 2000 V;  
Machine Model > 200 V  
16  
1
LVX  
LVX139G  
AWLYWW  
139  
ALYWG  
G
These Devices are Pb−Free and are RoHS Compliant  
1
2
3
4
5
6
7
SOIC−16  
TSSOP−16  
Y0a  
Y1a  
Y2a  
Y3a  
A0a  
A1a  
ADDRESS  
INPUTS  
ACTIVE−LOW  
OUTPUTS  
LVX139 = Specific Device Code  
= Assembly Location  
WL, L = Wafer Lot  
= Year  
A
Y
WW, W = Work Week  
G or G = Pb−Free Package  
1
Ea  
(Note: Microdot may be in either location)  
FUNCTION TABLE  
14  
13  
12  
11  
10  
9
Y0b  
Y1b  
Y2b  
Y3b  
ADDRESS  
INPUTS  
A0b  
A1b  
Inputs  
A1 A0  
Outputs  
ACTIVE−LOW  
OUTPUTS  
E
Y0 Y1 Y2 Y3  
H
L
L
L
L
X
L
L
H
H
X
L
H
L
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
L
15  
Eb  
H
H
Figure 1. Logic Diagram  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 5 of this data sheet.  
© Semiconductor Components Industries, LLC, 2014  
1
Publication Order Number:  
August, 2014 − Rev. 4  
MC74LVX139/D  

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