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MC74LVX139D PDF预览

MC74LVX139D

更新时间: 2024-09-30 05:22:11
品牌 Logo 应用领域
安森美 - ONSEMI 解码器解复用器
页数 文件大小 规格书
12页 152K
描述
Dual 2-to-4 Decoder/ Demultiplexer

MC74LVX139D 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP16,.25
针数:16Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.1系列:LV/LV-A/LVX/H
JESD-30 代码:R-PDSO-G16JESD-609代码:e0
长度:9.9 mm负载电容(CL):50 pF
逻辑集成电路类型:OTHER DECODER/DRIVER最大I(ol):0.004 A
功能数量:2端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:RAIL峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 VProp。Delay @ Nom-Sup:15 ns
传播延迟(tpd):18 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:Decoder/Drivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):2.7 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3.9 mm
Base Number Matches:1

MC74LVX139D 数据手册

 浏览型号MC74LVX139D的Datasheet PDF文件第2页浏览型号MC74LVX139D的Datasheet PDF文件第3页浏览型号MC74LVX139D的Datasheet PDF文件第4页浏览型号MC74LVX139D的Datasheet PDF文件第5页浏览型号MC74LVX139D的Datasheet PDF文件第6页浏览型号MC74LVX139D的Datasheet PDF文件第7页 
MC74LVX139  
Dual 2-to-4 Decoder/  
Demultiplexer  
The MC74LVX139 is an advanced high speed CMOS 2–to–4  
decoder/ demultiplexer fabricated with silicon gate CMOS technology.  
When the device is enabled (E = low), it can be used for gating or as  
a data input for demultiplexing operations. When the enable input is  
held high, all four outputs are fixed high, independent of other inputs.  
The inputs tolerate voltages up to 7 V, allowing the interface of 5 V  
systems to 3 V systems.  
http://onsemi.com  
MARKING DIAGRAMS  
16  
9
LVX139  
AWLYYWW  
High Speed: t = 6.0 ns (Typ) at V = 3.3 V  
PD  
CC  
SOIC–16  
D SUFFIX  
CASE 751B  
Low Power Dissipation: I = 4 µΑ (Max) at T = 25°C  
1
CC  
A
8
High Noise Immunity: V  
= V = 28% V  
NIL CC  
NIH  
16  
9
Power Down Protection Provided on Inputs  
Balanced Propagation Delays  
Designed for 2 V to 3.6 V Operating Range  
LVX139  
TSSOP–16  
DT SUFFIX  
CASE 948F  
AWLYWW  
Low Noise: V  
= 0.5 V (Max)  
OLP  
1
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300 mA  
8
16  
9
ESD Performance: HBM > 2000 V; Machine Model > 200 V  
Chip Complexity: 100 FETs or 25 Equivalent Gates  
LVX139  
ALYW  
SOIC EIAJ–16  
M SUFFIX  
CASE 966  
1
8
Ea  
1
2
16  
15  
V
CC  
A
= Assembly Location  
A0a  
Eb  
WL or L = Wafer Lot  
YY or Y = Year  
WW or W = Work Week  
3
4
14  
13  
A1a  
Y0a  
Y1a  
Y2a  
A0b  
A1b  
Y0b  
5
6
12  
11  
Y1b  
Y2b  
ORDERING INFORMATION  
7
8
10  
9
Y3a  
Device  
Package  
SO–16  
Shipping  
48 Units/Rail  
2500 Units/Reel  
GND  
Y3b  
MC74LVX139D  
MC74LVX139DR2  
MC74LVX139DT  
SO–16  
Figure 1. Pin Assignment  
TSSOP–16 96 Units/Rail  
MC74LVX139DTR2 TSSOP–16 2000 Units/Reel  
FUNCTION TABLE  
MC74LVX139M  
SO EIAJ–16 48 Units/Rail  
SO EIAJ–16 2000 Units/Reel  
Inputs  
A1 A0  
Outputs  
MC74LVX139MEL  
E
Y0 Y1 Y2 Y3  
H
L
L
L
L
X
L
L
H
H
X
L
H
L
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
L
H
H
Semiconductor Components Industries, LLC, 2001  
1
Publication Order Number:  
April, 2001 – Rev. 1  
MC74LVX139/D  

MC74LVX139D 替代型号

型号 品牌 替代类型 描述 数据表
74LV139D,112 NXP

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