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MC74HC4060 PDF预览

MC74HC4060

更新时间: 2024-09-25 23:01:35
品牌 Logo 应用领域
安森美 - ONSEMI 振荡器计数器
页数 文件大小 规格书
12页 208K
描述
14-Stage Binary Ripple Counter With Oscillator

MC74HC4060 数据手册

 浏览型号MC74HC4060的Datasheet PDF文件第2页浏览型号MC74HC4060的Datasheet PDF文件第3页浏览型号MC74HC4060的Datasheet PDF文件第4页浏览型号MC74HC4060的Datasheet PDF文件第5页浏览型号MC74HC4060的Datasheet PDF文件第6页浏览型号MC74HC4060的Datasheet PDF文件第7页 
High–Performance Silicon–Gate CMOS  
The MC74C4060A is identical in pinout to the standard CMOS  
MC14060B. The device inputs are compatible with standard CMOS  
outputs; with pullup resistors, they are compatible with LSTTL  
outputs.  
This device consists of 14 master–slave flip–flops and an oscillator  
with a frequency that is controlled either by a crystal or by an RC  
circuit connected externally. The output of each flip–flop feeds the  
next and the frequency at each output is half of that of the preceding  
one. The state of the counter advances on the negative–going edge of  
the Osc In. The active–high Reset is asynchronous and disables the  
oscillator to allow very low power consumption during stand–by  
operation.  
http://onsemi.com  
MARKING  
DIAGRAMS  
16  
PDIP–16  
N SUFFIX  
CASE 648  
MC74HC4060AN  
AWLYYWW  
16  
16  
1
1
16  
SO–16  
D SUFFIX  
CASE 751B  
HC4060A  
AWLYWW  
State changes of the Q outputs do not occur simultaneously because  
of internal ripple delays. Therefore, decoded output signals are subject  
to decoding spikes and may have to be gated with Osc Out 2 of the  
HC4060A.  
1
1
16  
HC40  
60A  
ALYW  
TSSOP–16  
DT SUFFIX  
CASE 948F  
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
16  
1
1
A
= Assembly Location  
WL = Wafer Lot  
YY = Year  
Low Input Current: 1 µA  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance With JEDEC Standard No. 7A Requirements  
Chip Complexity: 390 FETs or 97.5 Equivalent Gates  
WW = Work Week  
LOGIC DIAGRAM  
Osc Out 1 Osc Out 2  
10  
9
Pinout: 16–Lead Plastic Package (Top View)  
Osc Osc  
Out 1 Out 2  
Q9 Reset Osc In  
7
5
4
Q4  
Q5  
Q6  
Q7  
Q8  
Q9  
Q10  
Q12  
Q13  
Q14  
V
Q10 Q8  
15 14  
CC  
16  
13  
12  
11  
10  
9
11  
Osc In  
6
14  
13  
15  
1
2
3
1
2
3
4
5
6
7
8
GND  
Q12 Q13 Q14 Q6  
Q5  
Q7  
Q4  
12  
Pin 16 = V  
CC  
Pin 8 = GND  
Reset  
FUNCTION TABLE  
Clock  
Reset  
Output State  
L
L
No Charge  
ORDERING INFORMATION  
Advance to Next State  
All Outputs Are Low  
Device  
Package  
PDIP–16  
SOIC–16  
SOIC–16  
TSSOP–16  
Shipping  
X
H
MC74HC4060AN  
MC74HC4060AD  
MC74HC4060ADR2  
MC74HC4060ADT  
MC74HC4060ADTR2  
2000 / Box  
48 / Rail  
2500 / Reel  
96 / Rail  
TSSOP–16 2500 / Reel  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
March, 2000 – Rev. 2  
MC74HC4060A/D  

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IC,COUNTER,UP,14-BIT BINARY,HC-CMOS,TSSOP,16PIN,PLASTIC