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MC74HC390

更新时间： 2024-01-15 11:54:16
品牌 Logo 应用领域
安森美 - ONSEMI 计数器
页数 文件大小 规格书
8页 207K
描述
Dual 4-Stage Binary Ripple Counter with ±2 and ±5 Sections

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中文翻译

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MC74HC390 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：DIP, DIP16,.3Reach Compliance Code：unknown
风险等级：5.92计数方向：UP
JESD-30 代码：R-PDIP-T16JESD-609代码：e0
负载/预设输入：NO工作模式：ASYNCHRONOUS
功能数量：2端子数量：16
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP16,.3封装形状：RECTANGULAR
封装形式：IN-LINE电源：2/6 V
认证状态：Not Qualified子类别：Counters
表面贴装：NO技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL

MC74HC390 数据手册

 浏览型号MC74HC390的Datasheet PDF文件第2页浏览型号MC74HC390的Datasheet PDF文件第3页浏览型号MC74HC390的Datasheet PDF文件第4页浏览型号MC74HC390的Datasheet PDF文件第5页浏览型号MC74HC390的Datasheet PDF文件第6页浏览型号MC74HC390的Datasheet PDF文件第7页 
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High–Performance Silicon–Gate CMOS  
The MC74HC390A is identical in pinout to the LS390. The device  
inputs are compatible with standard CMOS outputs; with pullup  
resistors, they are compatible with LSTTL outputs.  
This device consists of two independent 4–bit counters, each  
composed of a divide–by–two and a divide–by–five section. The  
divide–by–two and divide–by–five counters have separate clock  
inputs, and can be cascaded to implement various combinations of ÷ 2  
and/or ÷ 5 up to a ÷ 100 counter.  
Flip–flops internal to the counters are triggered by high–to–low  
transitions of the clock input. A separate, asynchronous reset is  
provided for each 4–bit counter. State changes of the Q outputs do not  
occur simultaneously because of internal ripple delays. Therefore,  
decoded output signals are subject to decoding spikes and should not  
be used as clocks or strobes except when gated with the Clock of the  
HC390A.  
http://onsemi.com  
MARKING  
DIAGRAMS  
16  
PDIP–16  
N SUFFIX  
CASE 648  
MC74HC390AN  
AWLYYWW  
16  
16  
1
1
16  
SO–16  
D SUFFIX  
CASE 751B  
HC390A  
AWLYWW  
1
1
16  
HC  
390A  
ALYW  
TSSOP–16  
DT SUFFIX  
CASE 948F  
• Output Drive Capability: 10 LSTTL Loads  
• Outputs Directly Interface to CMOS, NMOS, and TTL  
• Operating Voltage Range: 2 to 6 V  
16  
1
1
• Low Input Current: 1 µA  
A
= Assembly Location  
WL = Wafer Lot  
YY = Year  
WW = Work Week  
• High Noise Immunity Characteristic of CMOS Devices  
• In Compliance with the Requirements Defined by JEDEC Standard  
No 7A  
• Chip Complexity: 244 FETs or 61 Equivalent Gates  
PIN ASSIGNMENT  
LOGIC DIAGRAM  
CLOCK A  
1
2
3
4
5
6
7
8
16  
15  
V
a
CC  
CLOCK A  
RESET a  
b
÷ 2  
COUNTER  
3, 13  
1, 15  
Q
A
CLOCK A  
Q
Aa  
14 RESET b  
13  
12 CLOCK B  
CLOCK B  
Q
Ab  
a
Q
Ba  
b
5, 11  
Q
Ca  
11  
10  
9
Q
Bb  
Q
B
Q
C
Q
D
÷ 5  
COUNTER  
6, 10  
7, 9  
4, 12  
2, 14  
Q
Da  
Q
Cb  
CLOCK B  
RESET  
GND  
Q
Db  
PIN 16 = V  
PIN 8 = GND  
CC  
FUNCTION TABLE  
ORDERING INFORMATION  
Clock  
Device  
Package  
PDIP–16  
SOIC–16  
SOIC–16  
TSSOP–16  
Shipping  
2000 / Box  
48 / Rail  
A
B
Reset  
Action  
MC74HC390AN  
X
X
H
Reset  
÷ 2 and ÷ 5  
MC74HC390AD  
X
L
L
Increment  
MC74HC390ADR2  
MC74HC390ADT  
MC74HC390ADTR2  
2500 / Reel  
96 / Rail  
÷ 2  
X
Increment  
÷ 5  
TSSOP–16 2500 / Reel  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
March, 2000 – Rev. 2  
MC74HC390A/D  
12345678

中文翻译

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