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MC74HC241ADW PDF预览

MC74HC241ADW

更新时间: 2024-01-06 23:26:29
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 总线驱动器总线收发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
7页 154K
描述
Octal 3-State Noninverting Buffer/Line Driver/Line Receiver

MC74HC241ADW 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP20,.3Reach Compliance Code:unknown
风险等级:5.92控制类型:ENABLE LOW/HIGH
JESD-30 代码:R-PDIP-T20JESD-609代码:e0
逻辑集成电路类型:BUS DRIVER位数:4
功能数量:2端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP20,.3封装形状:RECTANGULAR
封装形式:IN-LINE电源:2/6 V
认证状态:Not Qualified子类别:Bus Driver/Transceivers
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUALBase Number Matches:1

MC74HC241ADW 数据手册

 浏览型号MC74HC241ADW的Datasheet PDF文件第1页浏览型号MC74HC241ADW的Datasheet PDF文件第2页浏览型号MC74HC241ADW的Datasheet PDF文件第3页浏览型号MC74HC241ADW的Datasheet PDF文件第5页浏览型号MC74HC241ADW的Datasheet PDF文件第6页浏览型号MC74HC241ADW的Datasheet PDF文件第7页 
MC54/74HC241A  
SWITCHING WAVEFORMS  
V
CC  
ENABLE A  
50%  
50%  
GND  
t
t
f
r
V
CC  
V
DATA INPUT  
A OR B  
CC  
90%  
50%  
10%  
ENABLE B  
OUTPUT Y  
GND  
GND  
t
t
PLZ  
PZL  
t
t
HIGH  
PLH  
PHL  
IMPEDANCE  
90%  
50%  
10%  
OUTPUT  
YA OR YB  
50%  
10%  
90%  
V
OL  
t
t
PHZ  
PZH  
t
t
THL  
TLH  
V
OH  
50%  
OUTPUT Y  
HIGH  
IMPEDANCE  
Figure 1.  
Figure 2.  
TEST POINT  
TEST POINT  
1 k  
OUTPUT  
CONNECT TO V  
WHEN  
.
PZL  
CC  
AND t  
OUTPUT  
TESTING t  
PLZ  
CONNECT TO GND WHEN  
TESTING t AND t  
DEVICE  
UNDER  
TEST  
DEVICE  
UNDER  
TEST  
.
PZH  
PHZ  
C *  
C *  
L
L
* Includes all probe and jig capacitance  
* Includes all probe and jig capacitance  
Figure 3. Test Circuit  
Figure 4. Test Circuit  
PIN DESCRIPTIONS  
INPUTS  
Enable 8 (Pin 19)  
Output enable (active–high). When a high level is applied  
to this pin, the outputs of the “B” devices are enabled and the  
devices function as noninverting buffers. When a low level is  
applied, the outputs assume the high–impedance state.  
A1, A2, A3, A4, B1, B2, B3, B4  
(Pins 2, 4, 6, 8, 11, 13, 15, 17)  
Data input pins. Data on these pins appear in noninverted  
form on the corresponding Y outputs when the outputs are  
enabled.  
OUTPUTS  
CONTROLS  
YA1, YA2, YA3, YA4, YB1, YB2, YB3, YB4  
(Pins 18, 16, 14, 12, 9, 7, 5, 3)  
Enable A (Pin 1)  
Output enable (active–low). When a low level is applied to  
this pin, the outputs of the “A” devices are enabled and the  
devices function as noninverting buffers. When a high level is  
applied, the outputs assume the high–impedance state.  
Device outputs. Depending upon the state of the output–  
enable pins, these outputs are either noninverting outputs or  
high–impedance outputs.  
MOTOROLA  
4

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