MC74HC11NDS

更新时间： 2024-01-15 20:59:08

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		触发器
页数	文件大小	规格书
6页	214K
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数据手册

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MC74HC11NDS 数据手册

SEMICONDUCTOR TECHNICAL DATA

High–Performance Silicon–Gate CMOS

N SUFFIX

PLASTIC PACKAGE

CASE 648–08

The MC74HC112 is identical in pinout to the LS112. The device inputs are

compatible with standard CMOS outputs; with pullup resistors, they are

compatible with LSTTL outputs.

Each flip–flop is negative–edge clocked and has active–low asynchro-

nous Set and Reset inputs.

The HC112 is identical in function to the HC76, but has a different pinout.

D SUFFIX

SOIC PACKAGE

CASE 751B–05

•

Output Drive Capability: 10 LSTTL Loads

Outputs Directly Interface to CMOS, NMOS, and TTL

Operating Voltage Range: 2 to 6 V

DT SUFFIX

TSSOP PACKAGE

CASE 948F–01

Low Input Current: 1 µA

High Noise Immunity Characteristic of CMOS Devices

In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

ORDERING INFORMATION

•

Similar in Function to the LS112 Except When Set and Reset are Low

Simultaneously

Chip Complexity: 100 FETs or 25 Equivalent Gates

MC74HCXXXN

MC74HCXXXD

MC74HCXXXDT

Plastic

SOIC

TSSOP

PIN ASSIGNMENT

LOGIC DIAGRAM

CLOCK 1

RESET 1

SET 1

RESET 2

CLOCK 2

SET 1

CLOCK 1

SET 2

RESET 1

GND

FUNCTION TABLE

Inputs

SET 2

Outputs

Set Reset Clock

CLOCK 2

No Change

RESET 2

Toggle

PIN 16 = V

PIN 8 = GND

No Change

* Both outputs will remain low as long as Set and

Reset are low, but the output states are unpre-

dictable if Set and Reset go high simultaneously.

10/95

REV 6

Motorola, Inc. 1995

12 3 4 5 6

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