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MC74HC125A PDF预览

MC74HC125A

更新时间: 2024-01-05 07:25:41
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA /
页数 文件大小 规格书
6页 148K
描述
Quad 3-State Noninverting Buffers

MC74HC125A 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
High–Performance Silicon–Gate CMOS  
The MC74HC125A and MC74HC126A are identical in pinout to the LS125  
and LS126. The device inputs are compatible with standard CMOS outputs;  
with pullup resistors, they are compatible with LSTTL outputs.  
The HC125A and HC126A noninverting buffers are designed to be used  
with 3–state memory address drivers, clock drivers, and other bus–oriented  
systems. The devices have four separate output enables that are active–low  
(HC125A) or active–high (HC126A).  
N SUFFIX  
14–LEAD PLASTIC DIP PACKAGE  
CASE 646–06  
Output Drive Capability: 15 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2.0 to 6.0 V  
Low Input Current: 1.0 µA  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
D SUFFIX  
14–LEAD PLASTIC SOIC PACKAGE  
CASE 751A–03  
Chip Complexity: 72 FETs or 18 Equivalent Gates  
LOGIC DIAGRAM  
DT SUFFIX  
14–LEAD PLASTIC TSSOP PACKAGE  
CASE 948G–01  
HC125A  
Active–Low Output Enables  
HC126A  
Active–High Output Enables  
2
1
5
4
3
2
1
5
4
3
ORDERING INFORMATION  
A1  
A1  
Y1  
Y1  
MC74HCXXXAN  
MC74HCXXXAD  
Plastic  
SOIC  
OE1  
OE1  
MC74HCXXXADT TSSOP  
6
6
Y2  
Y3  
A2  
Y2  
Y3  
A2  
PIN ASSIGNMENT  
OE2  
OE2  
OE1  
A1  
1
2
14  
13  
V
CC  
9
10  
12  
13  
8
9
10  
12  
13  
8
OE4  
A3  
A3  
Y1  
3
4
12  
11  
A4  
Y4  
OE3  
OE3  
OE2  
A2  
Y2  
5
6
10  
9
OE3  
A3  
11  
11  
Y4  
A4  
Y4  
A4  
GND  
7
8
Y3  
OE4  
OE4  
PIN 14 = V  
CC  
PIN 7 = GND  
FUNCTION TABLE  
HC125A  
HC126A  
Inputs Output  
Inputs Output  
A
OE  
Y
A
OE  
Y
H
L
X
L
L
H
H
L
Z
H
L
X
H
H
L
H
L
Z
4/97  
Motorola, Inc. 1997  
REV 8  

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