Datasheet > MC7447RX1267LB

MC7447RX1267LB

更新时间： 2023-01-03 05:19:53

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		/
页数	文件大小	规格书
87页	1523K
描述
RISC Microprocessor, 32-Bit, 1267MHz, CMOS, CBGA360, 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, FLIP CHIP, BGA-360

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MC7447RX1267LB 数据手册

Advance Information

MPC7457EC

Rev. 4, 11/2003

MPC7457

RISC Microprocessor

Hardware Specifications

This hardware specification is primarily concerned with the PowerPC™ MPC7457; however,

unless otherwise noted, all information here also applies to the MPC7447. The MPC7457 and

MPC7447 are implementations of the PowerPC microprocessor family of reduced instruction

set computer (RISC) microprocessors. This hardware specification describes pertinent

electrical and physical characteristics of the MPC7457. For functional characteristics of the

processor, refer to the MPC7450 RISC Microprocessor Family User’s Manual.

This hardware specification contains the following topics:

Topic

Page

Section 1.1, “Overview”

Section 1.2, “Features”

Section 1.3, “Comparison with the MPC7455, MPC7445, MPC7450, MPC7451,

and MPC7441”

Section 1.4, “General Parameters”

Section 1.5, “Electrical and Thermal Characteristics”

Section 1.6, “Pin Assignments”

Section 1.7, “Pinout Listings”

Section 1.8, “Package Description”

Section 1.9, “System Design Information”

Section 1.10, “Document Revision History”

Section 1.11, “Ordering Information”

To locate any published updates for this hardware specification, refer to the website at

http://www.motorola.com/semiconductors.

1.1 Overview

The MPC7457 is the fourth implementation of the fourth generation (G4) microprocessors

from Motorola. The MPC7457 implements the full PowerPC 32-bit architecture and is

targeted at networking and computing systems applications. The MPC7457 consists of a

processor core, a 512-Kbyte L2, and an internal L3 tag and controller that support a glueless

backside L3 cache through a dedicated high-bandwidth interface. The MPC7447 is identical

to the MPC7457 except that it does not support the L3 cache interface.

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