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MC14046BFL2 PDF预览

MC14046BFL2

更新时间： 2024-01-10 00:08:21
品牌 Logo 应用领域
安森美 - ONSEMI 光电二极管
页数 文件大小 规格书
8页 108K
描述
PHASE LOCKED LOOP, 1.9MHz, PDSO16, EIAJ, PLASTIC, SOIC-16

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MC14046BFL2 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SOIC包装说明：SOP, SOP16,.3
针数：16Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.7
模拟集成电路 - 其他类型：PHASE LOCKED LOOPJESD-30 代码：R-PDSO-G16
JESD-609代码：e4长度：10.2 mm
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP16,.3封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5/15 V认证状态：Not Qualified
座面最大高度：2.05 mm子类别：PLL or Frequency Synthesis Circuits
最大供电电压 (Vsup)：18 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：5.275 mm
Base Number Matches：1

MC14046BFL2 数据手册

 浏览型号MC14046BFL2的Datasheet PDF文件第2页浏览型号MC14046BFL2的Datasheet PDF文件第3页浏览型号MC14046BFL2的Datasheet PDF文件第4页浏览型号MC14046BFL2的Datasheet PDF文件第5页浏览型号MC14046BFL2的Datasheet PDF文件第6页浏览型号MC14046BFL2的Datasheet PDF文件第7页 
MC14046B  
Phase Locked Loop  
The MC14046B phase locked loop contains two phase comparators,  
a voltage–controlled oscillator (VCO), source follower, and zener  
diode. The comparators have two common signal inputs, PCA and  
in  
PCB . Input PCA can be used directly coupled to large voltage  
in  
in  
signals, or indirectly coupled (with a series capacitor) to small voltage  
signals. The self–bias circuit adjusts small voltage signals in the linear  
region of the amplifier. Phase comparator 1 (an exclusive OR gate)  
http://onsemi.com  
MARKING  
DIAGRAMS  
16  
provides a digital error signal PC1 , and maintains 90° phase shift at  
out  
the center frequency between PCA and PCB signals (both at 50%  
in  
in  
duty cycle). Phase comparator 2 (with leading edge sensing logic)  
provides digital error signals, PC2 and LD, and maintains a 0°  
PDIP–16  
P SUFFIX  
CASE 648  
MC14046BCP  
AWLYYWW  
out  
phase shift between PCA and PCB signals (duty cycle is  
in  
in  
1
immaterial). The linear VCO produces an output signal VCO  
out  
16  
whose frequency is determined by the voltage of input VCO and the  
in  
capacitor and resistors connected to pins C1 , C1 , R1, and R2. The  
A
B
14046B  
SO–16  
DW SUFFIX  
CASE 751G  
source–follower output SF with an external resistor is used where  
out  
the VCO signal is needed but no loading can be tolerated. The inhibit  
in  
AWLYYWW  
input Inh, when high, disables the VCO and source follower to  
minimize standby power consumption. The zener diode can be used to  
assist in power supply regulation.  
1
16  
Applications include FM and FSK modulation and demodulation,  
frequency synthesis and multiplication, frequency discrimination,  
tone decoding, data synchronization and conditioning,  
voltage–to–frequency conversion and motor speed control.  
EIAJ SO–16  
F SUFFIX  
CASE 966  
MC14046B  
ALYW  
1
• Buffered Outputs Compatible with MHTL and Low–Power TTL  
• Diode Protection on All Inputs  
• Supply Voltage Range = 3.0 to 18 V  
A
WL, L  
YY, Y  
= Assembly Location  
= Wafer Lot  
= Year  
WW, W = Work Week  
• Pin–for–Pin Replacement for CD4046B  
• Phase Comparator 1 is an Exclusive Or Gate and is Duty Cycle Limited  
ORDERING INFORMATION  
• Phase Comparator 2 switches on Rising Edges and is not Duty Cycle  
Device  
Package  
PDIP–16  
SO–16  
Shipping  
Limited  
MC14046BCP  
MC14046BDW  
MC14046BDWR2  
2000/Box  
2350/Box  
MAXIMUM RATINGS (Voltages Referenced to V ) (Note 2.)  
SS  
Symbol  
Parameter  
Value  
Unit  
V
SO–16  
1000/Tape & Reel  
V
DD  
DC Supply Voltage Range  
Input Voltage Range (All Inputs)  
DC Input Current, per Pin  
–0.5 to +18.0  
MC14046BF  
EIAJ SO–16 Refer to Note 1.  
EIAJ SO–16 Refer to Note 1.  
V
in  
–0.5 to V + 0.5  
V
DD  
MC14046BFEL  
I
in  
±10  
mA  
mW  
1. For ordering information on the EIAJ version of  
the SOIC packages, please contact your local  
ON Semiconductor representative.  
P
D
Power Dissipation,  
500  
per Package (Note 3.)  
T
Operating Temperature Range  
Storage Temperature Range  
–55 to +125  
–65 to +150  
°C  
°C  
A
This device contains protection circuitry to guard  
against damage due to high static voltages or electric  
fields. However, precautions must be taken to avoid ap-  
plications of any voltage higher than maximum rated  
voltages to this high–impedance circuit. For proper  
T
stg  
2. Maximum Ratings are those values beyond which damage to the device  
may occur.  
3. Temperature Derating:  
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C  
operation, V and V should be constrained to the  
in  
out  
range V v (V or V ) v V .  
DD  
SS  
in  
out  
Unused inputs must always be tied to an appropriate  
logic voltage level (e.g., either V or V ). Unused out-  
SS  
DD  
puts must be left open.  
Semiconductor Components Industries, LLC, 2001  
1
Publication Order Number:  
May, 2001 – Rev. 7  
MC14046B/D  
12345678

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