MC13144
APPLICATIONS INFORMATION
Evaluation PC Board
f = 1900 mHz
The evaluation PCB is very versatile and is intended to
be used across the entire useful frequency range of this
device. The PC board layout accommodates all SMT
components on the circuit side (see Circuit Side Component
Placement View).
I
/Gain
En2 Low
En2 High
CC
En1 Low
En1 High
0 mA/–22 dB
3.4 mA/10 dB
1.2 mA/7.5 dB
8.2 mA/13 dB
Component Selection
Input/Output Matching
The evaluation PC board is laid out for the 4DFA (2 pole
SMD Type) and 4DFB (3 pole SMD Type) filters which are
available for applications in Cellular and GSM, GPS (1.2 to
1.5 GHz), DECT, PHS and PCS (1.8 to 2.0 GHz) and
ISM Bands (902 to 928 MHz and 2.4 to 2.5 GHz). In the
926.5 MHz Application Circuit, a ceramic deielectric filter
is used (Toko part # 4DFA–926A10).
A typical application at 900 MHz yields 17 dB gain and
1.4 dB noise figure. In this circuit a series inductor of 5.6 nH
is used to match the input and a shunt inductor of 8.2 nH
which also serves as an RFC and a series capacitor of 0.9 p
is used to match the LNA output to 50 Ω load impedance.
It may be desirable to use a RF ceramic or SAW filter after
the LNA when driving a mixer to provide image frequency
rejection. The image filter is selected based on cost, size and
performance tradeoffs. Typical RF filters have 3.0 to 5.0 dB
insertion loss. Interface matching between the RF input, RF
filter and the mixer is shown in Application Circuit and the
Component Placement View.
A typical application at 1900 MHz yields 13 dB gain and
2.7 dB noise figure. In this circuit a series inductor of 5.6 nH
and a series capacitor of 1.0 pF are used to match the input
and a shut inductor of 2.0 nH and a series capacitor of 2.0 pF
are used to match the LNA output to 50 Ω load impedance.
LNA Input/Output
The LNA input impedance is the base of a common emitter
cascode amplifier. The LNA output is the collector of the
cascode stage and it is loaded with a series resistor of 400 Ω
and a capacitor of 10 pF to provide stability.
Digitally Programmable Bias/Enable
The LNA is enabled by a 2 bit (En1 and En2)
programmable bias circuit. The internal circuit shows the
comparator circuit which programs the internal regulator. The
logic table below shows the bias and typical performance.
f = 900 mHz
I
/Gain
En2 Low
En2 High
CC
En1 Low
En1 High
0 mA/–22 dB
3.4 mA/13 dB
1.2 mA/9.2 dB
9.4 mA/17 dB
Figure 2. MC13144D Application Circuit
(926.5 MHz)
En1 En2
V
CC
39 nH
8.2 nH
100 p
Toko
Ceramic
Filter
RF
Output
1.0 M
0.4 p
8
1
7
6
5
4
8.2 nH
MC13144D
47
2
3
47 p
V
CC
RF
Input
100 n
100 p
5.6 nH
4
MOTOROLA ANALOG IC DEVICE DATA