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MC10E1651_06 PDF预览

MC10E1651_06

更新时间: 2024-01-12 09:51:49
品牌 Logo 应用领域
安森美 - ONSEMI 锁存器比较器
页数 文件大小 规格书
10页 136K
描述
5V, −5V Dual ECL Output Comparator with Latch

MC10E1651_06 数据手册

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MC10E1651  
5V, 5V Dual ECL Output  
Comparator with Latch  
The MC10E1651 is fabricated using ON Semiconductor’s  
advanced MOSAIC IIIprocess. The MC10E1651 incorporates a  
fixed level of input hysteresis as well as output compatibility with 10  
KH logic devices. In addition, a latch is available allowing a sample  
and hold function to be performed. The device is available in both a  
16-pin DIP and a 20-pin surface mount package.  
http://onsemi.com  
MARKING  
DIAGRAMS  
The latch enable (LEN and LEN ) input pins operate from standard  
a
b
ECL 10 KH logic levels. When the latch enable is at a logic high level,  
the MC10E1651 acts as a comparator; hence, Q will be at a logic high  
level if V1 > V2 (V1 is more positive than V2). Q is the complement  
of Q. When the latch enable input goes to a low logic level, the outputs  
are latched in their present state providing the latch enable setup and  
hold time constraints are met.  
16  
MC10E1651L  
AWLYYWW  
1
CDIP16  
L SUFFIX  
CASE 620A  
Features  
Typical 3.0 dB Bandwidth > 1.0 GHz  
Typical V to Q Propagation Delay of 775 ps  
Typical Output Rise/Fall of 350 ps  
Common Mode Range 2.0 V to +3.0 V  
Individual Latch Enables  
1 20  
MC10E  
1651FNG  
AWLYYWW  
20  
1
Differential Outputs  
28 mV Input Hysteresis  
PLCC20  
FN SUFFIX  
CASE 775  
Operating Mode: V = 5.0 V, V = 5.2 V, GND = 0 V  
CC  
EE  
No Internal Input Pulldown Resistors  
ESD Protection: > 2 kV Human Body Model,  
> 100 V Machine Model  
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test  
Moisture Sensitivity Level 1  
A
= Assembly Location  
= Wafer Lot  
= Year  
= Work Week  
= PbFree Package  
WL  
YY  
WW  
G
For Additional Information, see Application Note AND8003/D  
Flammability Rating: UL 94 V0 @ 0.125 in,  
Oxygen Index: 28 to 34  
Transistor Count = 85 devices  
PbFree Packages are Available*  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 7 of this data sheet.  
*For additional information on our PbFree strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
November, 2006 Rev. 8  
MC10E1651/D  

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