MC10E1652

更新时间： 2024-01-19 17:38:36

品牌	Logo	应用领域
安森美 - ONSEMI		比较器输出元件
页数	文件大小	规格书
7页	143K
描述
DUAL ECL OUTPUT COMPARATOR WITH LATCH

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数据手册

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MC10E1652 数据手册

SEMICONDUCTOR TECHNICAL DATA

The MC10E1652 is functionally and pin-for-pin compatible with the

MC10E1651 and thus the MC1651 in the MECL III family, but is

fabricated using Motorola’s advanced MOSAIC III processand is output

compatible with 10H logic devices. In addition, the device is available in

both a 16-pin DIP and a 20-pin surface mount package. However, the

MC10E1652 provides user programmable hysteresis.

DUAL ECL OUTPUT

COMPARATOR

WITH LATCH

The latch enable (LEN and LEN ) input pins operate from standard

ECL 10H logic levels. When the latch enable is at a logic high level the

MC10E1652 acts as a comparator, hence Q will be at a logic high level if

V1 > V2 (V1 is more positive than V2). Q is the complement of Q. When

the latch enable input goes to a low logic level, the outputs are latched in

their present state, providing the latch enable setup and hold time

constraints are met. The level of input hysteresis is controlled by applying

a bias voltage to the HYS pin.

• Typical 3.0 dB Bandwidth > 1.0 GHz

• Typical V to Q Propagation Delay of 775 ps

• Typical Output Rise/Fall of 350 ps

• Common Mode Range –2.0 V to +3.0 V

• Individual Latch Enables

FN SUFFIX

PLASTIC PACKAGE

CASE 775-02

• Differential Outputs

• Programmable Input Hysteresis

L SUFFIX

CERAMIC PACKAGE

CASE 620-10

LOGIC DIAGRAM

FUNCTION TABLE

LEN

V1, V2

Function

V1a

V1 > V2

V1 < V2

V2a

Latched

LEN

HYS

V1b

V2b

LEN

= –5.2 V

= +5.0 V

12/93

Motorola, Inc. 1996

REV 1

2–1

12 3 4 5 6 7

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