SEMICONDUCTOR TECHNICAL DATA
The MC10E/100E141 is an 8-bit full-function shift register. The E141
performs serial/parallel in and serial/parallel out, shifting in either
direction. The eight inputs D – D accept parallel input data, while
0
7
DL/DR accept serial input data for left/right shifting. The Qn outputs do
not need to be terminated for the shift operation to function. To minimize
noise and power, any Q output not used should be left unterminated.
• 700MHz Min. Shift Frequency
• 8-Bit
8-BIT SHIFT
REGISTER
• Full-Function, Bi-Directional
• Asynchronous Master Reset
• Pin-Compatible with E241
• Extended 100E V
EE
Range of – 4.2V to – 5.46V
• 75kΩ Input Pulldown Resistors
The select pins, SEL0 and SEL1, select one of four modes of
operation: Load, Hold, Shift Left, Shift Right, according to the Function
Table.
Input data is accepted a set-up time before the positive clock edge. A
HIGH on the Master Reset (MR) pin asynchronously resets all the
registers to zero.
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
Pinout: 28-Lead PLCC (Top View)
SEL0
DL
D
D
D
V
Q
7
7
6
5
CCO
25
24
23
22
21
20
19
SEL1
Q
Q
26
18
17
16
15
14
13
6
FUNCTION TABLE
CLK
MR
27
28
5
SEL0
SEL1
Function
V
CC
L
L
H
H
L
H
L
Load
Shift Right (D to D
)
n+1
n
V
1
2
NC
EE
Shift Left (D to D
)
n –1
n
H
Hold
DR
V
CCO
PIN NAMES
Pin
D
0
3
Q
4
3
Function
D
1
4
Q
12
D
– D
Parallel Data Inputs
Serial Data Inputs
Mode Select In Inputs
Clock
0
7
DL, DR
SEL0, SEL1
CLK
5
6
7
8
9
10
11
D
D
D
V
Q
Q
Q
2
2
3
4
CCO
0
1
Q
MR
– Q
Data Outputs
Master Reset
0
7
* All V
and V pins are tied together on the die.
CCO
CC
EXPANDED FUNCTION TABLE
Function
DL
DR
SEL0
SEL1
MR
CLK
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Load
X
X
X
L
X
L
L
L
L
H
H
L
L
L
L
L
L
L
Z
Z
Z
Z
Z
Z
D0
L
D1
Q0
L
D2
Q1
Q0
Q1
Q2
Q2
D3
Q2
Q1
Q2
Q3
Q3
D4
Q3
Q2
Q3
Q4
Q4
D5
Q4
Q3
Q4
Q5
Q5
D6
D7
Q6
Q5
L
Shift Right
Q5
Q4
Q5
L
H
X
X
X
L
H
Shift Left
Hold
H
H
H
L
Q0
Q1
Q1
H
X
L
Q0
Q0
H
H
L
H
X
X
X
X
H
X
H
X
L
Z
X
Q0
L
Q1
L
Q2
L
Q3
L
Q4
L
Q5
L
L
L
H
L
Reset
H
7/96
Motorola, Inc. 1996
REV 3
2–1