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MC10E143FN PDF预览

MC10E143FN

更新时间: 2024-02-21 23:10:22
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA /
页数 文件大小 规格书
4页 112K
描述
9-BIT HOLD REGISTER

MC10E143FN 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QLCC包装说明:LEAD FREE, PLASTIC, LCC-28
针数:28Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.7
其他特性:NECL MODE: VCC = 0V WITH VEE = -4.2V TO -5.7V系列:10E
JESD-30 代码:S-PQCC-J28JESD-609代码:e3
长度:11.505 mm逻辑集成电路类型:D FLIP-FLOP
湿度敏感等级:3位数:9
功能数量:1端子数量:28
最高工作温度:85 °C最低工作温度:
输出特性:OPEN-EMITTER输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):260传播延迟(tpd):1 ns
认证状态:Not Qualified座面最大高度:4.57 mm
最大供电电压 (Vsup):5.7 V最小供电电压 (Vsup):4.2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:ECL温度等级:OTHER
端子面层:Tin (Sn)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40触发器类型:POSITIVE EDGE
宽度:11.505 mm最小 fmax:700 MHz
Base Number Matches:1

MC10E143FN 数据手册

 浏览型号MC10E143FN的Datasheet PDF文件第2页浏览型号MC10E143FN的Datasheet PDF文件第3页浏览型号MC10E143FN的Datasheet PDF文件第4页 
SEMICONDUCTOR TECHNICAL DATA  
The MC10E/100E143 is a 9-bit holding register, designed with  
byte-parity applications in mind. The E143 holds current data or loads  
new data, with the nine inputs D0 – D8 accepting parallel input data.  
700MHz Min. Operating Frequency  
9-Bit for Byte-Parity Applications  
Asynchronous Master Reset  
Dual Clocks  
9-BIT HOLD  
REGISTER  
Extended 100E V  
EE  
Range of – 4.2V to – 5.46V  
75kInput Pulldown Resistors  
The SEL (Select) input pin is used to switch between the two modes of  
operation — HOLD and LOAD. Input data is accepted by the registers a  
set-up time before the positive going edge of CLK1 or CLK2. A HIGH on  
the Master Reset pin (MR) asynchronously resets all the registers to zero.  
Pinout: 28-Lead PLCC (Top View)  
SEL  
D
D
D
D
V
Q
8
8
7
6
5
CCO  
FN SUFFIX  
PLASTIC PACKAGE  
CASE 776-02  
25  
24  
23  
22  
21  
20  
19  
MR  
CLK1  
CLK2  
18  
17  
16  
15  
14  
13  
26  
Q
Q
7
27  
28  
6
V
CC  
LOGIC DIAGRAM  
V
1
2
EE  
Q
D
Q
Q
Q
Q
5
0
1
2
3
MUX  
D
0
R
NC  
V
CCO  
D
D
0
3
Q
MUX  
4
3
D
D
D
R
1
2
3
D
1
4
12  
Q
D
MUX  
5
6
7
8
9
10  
11  
R
D
D
D
V
Q
Q
Q
2
2
3
4
CCO  
0
1
* All V  
and V  
CCO  
pins are tied together on the die.  
CC  
D
MUX  
R
PIN NAMES  
Pin  
Function  
D
SEL  
CLK1, CLK2  
MR  
– D  
Parallel Data Inputs  
Mode Select Input  
Clock Inputs  
0
8
Q
D
8
MUX  
R
D
8
Master Reset  
Q
– Q  
Data Outputs  
0
8
NC  
No Connection  
SEL  
FUNCTIONS  
SEL  
CLK1  
CLK2  
MR  
Mode  
L
H
Load  
Hold  
12/93  
REV 2  
Motorola, Inc. 1996  

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