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MC10195PD PDF预览

MC10195PD

更新时间: 2024-11-19 12:58:59
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 逻辑集成电路
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4页 106K
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MC10195PD 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC10195 is a Hex Buffer Inverter which is built using six EXCLUSIVE  
NOR gates. There is a common input to these gates which when placed low or  
left open allows them to act as inverters. With the common input connected to  
a high logic level the MC10195 is a hex buffer, useful for high fanout clock  
driving and reducing stub lengths on long bus lines.  
L SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
P
t
t
= 200 mW typ/pkg (No Load)  
= 2.8 ns typ (B–Q)  
= 3.8 ns typ (A–Q)  
D
pd  
pd  
t , t = 2.5 ns typ (20%–80%)  
r f  
P SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
FN SUFFIX  
PLCC  
CASE 775–02  
LOGIC DIAGRAM  
A
B
9
5
Q
2
DIP  
3
6
7
PIN ASSIGNMENT  
V
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
V
CC2  
CC1  
4
Q1  
Q6  
Q5  
Q4  
B6  
B5  
B4  
A
Q2  
Q3  
B1  
B2  
B3  
13  
14  
15  
10  
11  
12  
V
EE  
Pin assignment is for Dual–in–Line Package.  
For PLCC pin assignment, see the Pin Conversion  
Tables on page 6–36 of the Motorola MECL Data  
Book (DL122/D).  
V
V
V
= PIN 1  
= PIN 16  
= PIN 8  
CC1  
CC2  
EE  
TRUTH TABLE  
Inputs  
Output  
A
B
L
Q
H
L
L
L
H
L
H
H
L
H
H
3/93  
Motorola, Inc. 1996  
REV 5  

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