D a t a S h e e t
Interrupt (PC/PS saving)
6 cycles (16 priority levels)
The Harvard architecture allows simultaneous execution of program and data access.
Instruction compatibility with the FR family
Built-in memory protection function (MPU)
Eight protection areas can be specified commonly for instructions and data.
Control access privilege in both privilege mode and user mode
Built-in FPU (floating-point operation)
IEEE754 compliant
Floating-point register: 32 bits 16 sets
Peripheral Functions
Clock generation (SSCG function is available)
Main oscillation (4 MHz to 20 MHz)
PLL multiplication rate:1 to 32 times
CR oscillation
Oscillation frequency: 100kHz, with frequency precision 10%
Trimming is enabled
To be used as a count clock of hardware watchdog
Oscillation stop feature during standby is not available
MB91F583MJ/F584MJ/F585MJ/F583MK/F584MK/F585MK
MB91F583SJ/F584SJ/F585SJ/F583SK/F584SK/F585SK
Oscillation stop feature during standby is available
MB91F583MG/F584MG/F585MG/F583MH/F584MH/F585MH
MB91F583SG/F584SG/F585SG/F583SH/F584SH/F585SH
Built-in program flash memory capacity
MB91F583: 256+64 Kbytes
MB91F584: 384+64 Kbytes
MB91F585: 512+64 Kbytes
Built-in data flash (WorkFlash) 64 Kbytes
Built-in RAM capacity
Main RAM
MB91F583: 32 Kbytes
MB91F584: 48 Kbytes
MB91F585: 48 Kbytes
Backup RAM 8 Kbytes
General-purpose ports: MB91F583M/F584M/F585M
Including eight I2C pseudo open drain corresponding ports
MB91F583S/F584S/F585S 44ports
Including two I2C pseudo open drain corresponding ports
76 ports
DMA controller
Up to 8 channels can be started simultaneously.
2 transfer factors (Internal peripheral request and software)
External interrupt input
MB91F583M/F584M/F585M: 8 channels
MB91F583S/F584S/F585S: 7 channels
Level ("H" / "L") or edge detection (rising or falling) enabled
Multi-function serial communication (built-in transmission/reception FIFO memory)
MB91F583M/F584M/F585M: 4 channels
MB91F583S/F584S/F585S: 2 channels
UART (Asynchronous serial interface)
Full-duplex double buffering system, 64-byte transmission FIFO memory, 64-byte reception
FIFO memory
Parity or no parity is selectable.
Built-in dedicated baud rate generator
An external clock can be used as the transfer clock
Parity, frame, and overrun error detection functions provided
DMA transfer supported
2
MB91585MG_DS705-00013-1v1-E, January 31, 2014